141 lines
6.0 KiB
C
141 lines
6.0 KiB
C
/*
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* @brief LPC11u6x DMA ROM API declarations and functions
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2013
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __ROM_DMA_11U6X_H_
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#define __ROM_DMA_11U6X_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup CHIP_DMAROM_11U6X CHIP: LPC11U6X DMA ROM API declarations and functions
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* @ingroup ROMAPI_11U6X
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* @{
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*/
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/**
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* @brief LPC11U6X DMA ROM driver handle structure
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*/
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typedef void *DMA_HANDLE_T;
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/**
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* @brief LPC11U6X DMA ROM driver callback function
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* @param res0 : error code
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* @param res1 : 0 = INTA is issued, 1 = INTB is issued
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*/
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typedef void (*DMA_CALLBK_T)(uint32_t res0, uint32_t res1);
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/**
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* @brief LPC11U6X DMA ROM event values
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*/
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#define DMA_EVENT_SW_REQ 0
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#define DMA_EVENT_PERIPH_REQ 1
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#define DMA_EVENT_HW_REQ 2
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/**
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* @brief LPC11U6X DMA ROM hardware trigger values
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*/
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#define DMA_HWTRIG_BURST_SIZE(n) (n) /*!< Burst size is 2^n, n <= 15 */
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#define DMA_HWTRIG_SRC_BURST_WRAP (1 << 4) /*!< Source burst wrapping enabled */
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#define DMA_HWTRIG_TRIGGER_BURST (1 << 6) /*!< Hardware trigger cause a burst transfer */
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/**
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* @brief LPC11U6X DMA ROM channel configuration structure
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*/
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typedef struct DMA_CHANNEL {
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uint8_t event; /*!< Event type selection for DMA transfer, a value of DMA_EVENT_* types */
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uint8_t hd_trigger; /*!< In case hardware trigger is enabled, OR'ed values of type DMA_HWTRIG_* */
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uint8_t Priority; /*!< Priority level 0 - 7, 0 = lowest, 7 = highest */
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DMA_CALLBK_T callback_func_pt; /*!< Callback function, only invoked when INTA or INTB is enabled */
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} DMA_CHANNEL_T ;
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/**
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* @brief LPC11U6X DMA ROM task configuration values
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*/
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#define DMA_TASK_PINGPONG (1 << 0) /*!< Linked with previous task for Ping_Pong transfer */
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#define DMA_TASK_SWTRIG (1 << 1) /*!< The trigger for this channel is set immediately */
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#define DMA_TASK_CLEARTRIG (1 << 2) /*!< The trigger is cleared when this task is finished */
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#define DMA_TASK_SELINTA (1 << 3) /*!< The IntA flag for this channel will be set when this task is finished */
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#define DMA_TASK_SELINTB (1 << 4) /*!< The IntB flag for this channel will be set when this task is finished */
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/**
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* @brief LPC11U6X DMA ROM data type values
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*/
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#define DMA_DATA_SIZE(n) (n) /*!< Data width, 0: 8-bit, 1: 16-bit, 2: 32-bit, 3: reserved */
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/* DMA_DATA_SRCINC = 0 : The source address is not incremented for each transfer */
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/* DMA_DATA_SRCINC = 1 : The source address is incremented by the amount specified by Width for each transfer */
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/* DMA_DATA_SRCINC = 2 : The source address is incremented by 2 times the amount specified by Width for each transfer */
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/* DMA_DATA_SRCINC = 3 : The source address is incremented by 4 times the amount specified by Width for each transfer */
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#define DMA_DATA_SRCINC(n) (n << 2) /*!< Source address incrementation */
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/* DMA_DATA_DSTINC = 0 : The destination address is not incremented for each transfer */
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/* DMA_DATA_DSTINC = 1 : The destination address is incremented by the amount specified by Width for each transfer */
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/* DMA_DATA_DSTINC = 2 : The destination address is incremented by 2 times the amount specified by Width for each transfer */
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/* DMA_DATA_DSTINC = 3 : The destination address is incremented by 4 times the amount specified by Width for each transfer */
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#define DMA_DATA_DSTINC(n) (n << 4) /*!< Destination address incrementation */
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/**
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* @brief LPC11U6X DMA ROM task structure
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*/
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typedef struct DMA_TASK {
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uint8_t ch_num; /*!< DMA channel number */
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uint8_t config; /*!< Configuration of this task, OR'ed values of DMA_TASK_* */
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uint8_t data_type; /*!< Data type, OR'ed values of DMA_DATA_* */
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uint16_t data_length; /*!< 0: 1 transfer, 1: 2 transfer, <20> 1023: 1024 transfers */
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uint32_t src; /*!< Source data end address */
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uint32_t dst; /*!< Destination end address */
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uint32_t task_addr; /*!< the address of RAM for saving this task. Must be 16 butes and aligned on a 16 byte boundary */
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} DMA_TASK_T ;
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/**
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* LPC11U6X DMA ROM driver APIs structure
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*/
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typedef struct DMAD_API {
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void (*dma_isr)(DMA_HANDLE_T* handle);
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uint32_t (*dma_get_mem_size)( void);
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DMA_HANDLE_T* (*dma_setup)( uint32_t base_addr, uint8_t *ram );
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ErrorCode_t (*dma_init)( DMA_HANDLE_T* handle, DMA_CHANNEL_T *channel, DMA_TASK_T *task);
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ErrorCode_t (*dma_link)( DMA_HANDLE_T* handle, DMA_TASK_T *task, uint8_t valid);
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ErrorCode_t (*dma_set_valid)( DMA_HANDLE_T* handle, uint8_t chl_num);
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ErrorCode_t (*dma_pause)( DMA_HANDLE_T* handle, uint8_t chl_num);
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ErrorCode_t (*dma_unpause)( DMA_HANDLE_T* handle, uint8_t chl_num);
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ErrorCode_t (*dma_abort)( DMA_HANDLE_T* handle, uint8_t chl_num);
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} DMAD_API_T ;
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ROM_DMA_11U6X_H_ */
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