RedHawk
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07e4083ab8
28
source/shoh/src/Fmutex.cpp
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28
source/shoh/src/Fmutex.cpp
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@ -0,0 +1,28 @@
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/*
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* Fmutex.cpp
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*
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* Created on: 15.8.2017
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* Author: krl
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*/
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#include "Fmutex.h"
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Fmutex::Fmutex() {
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// TODO Auto-generated constructor stub
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mutex = xSemaphoreCreateMutex();
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}
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Fmutex::~Fmutex() {
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// TODO Auto-generated destructor stub
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vSemaphoreDelete(mutex);
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}
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void Fmutex::lock()
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{
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xSemaphoreTake(mutex, portMAX_DELAY);
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}
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void Fmutex::unlock()
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{
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xSemaphoreGive(mutex);
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}
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24
source/shoh/src/Fmutex.h
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24
source/shoh/src/Fmutex.h
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@ -0,0 +1,24 @@
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/*
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* Fmutex.h
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*
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* Created on: 15.8.2017
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* Author: krl
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*/
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#ifndef FMUTEX_H_
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#define FMUTEX_H_
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#include "FreeRTOS.h"
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#include "semphr.h"
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class Fmutex {
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public:
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Fmutex();
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virtual ~Fmutex();
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void lock();
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void unlock();
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private:
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SemaphoreHandle_t mutex;
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};
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#endif /* FMUTEX_H_ */
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@ -6,12 +6,17 @@
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#include "ThreadCommon.h"
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#include "Master.h"
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#include "Rotary.h"
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#include "retarget_uart.h"
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int main(void)
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{
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SystemCoreClockUpdate();
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Board_Init();
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retarget_init();
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printf("Hello there!\r\n");
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ThreadCommon::ThreadManager* manager = new ThreadCommon::ThreadManager;
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ThreadCommon::QueueManager* qmanager = new ThreadCommon::QueueManager;
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//Creating queues
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228
source/shoh/src/peripherals/LpcDebugUart.cpp
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228
source/shoh/src/peripherals/LpcDebugUart.cpp
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@ -0,0 +1,228 @@
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/*
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* LpcDebugUart.cpp
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*
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* Created on: 6.5.2023
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*/
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#include <cstring>
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#include <mutex>
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#include "LpcDebugUart.h"
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/* shoh: Important differences
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* We don't have movable pins -> not needed.
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*
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* USART0 (the only debug uart):
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* Chip_IOCON_PinMuxSet(LPC_IOCON, 0, 18, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN));
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* Chip_IOCON_PinMuxSet(LPC_IOCON, 0, 19, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN));
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*/
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static LpcDebugUart *u0;
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extern "C" {
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/**
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* @brief UART interrupt handler using ring buffers
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* @return Nothing
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*/
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void USART0_IRQHandler(void)
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{
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portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
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if(u0) {
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u0->isr(&xHigherPriorityTaskWoken);
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}
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portEND_SWITCHING_ISR(xHigherPriorityTaskWoken);
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}
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}
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void LpcDebugUart::isr(portBASE_TYPE *hpw) {
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// get interrupt status for notifications
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uint32_t istat = Chip_UART0_ReadLineStatus(uart);
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// chip library is used to handle receive and transmit
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Chip_UART0_IRQRBHandler(uart, &rxring, &txring);
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// notify (hopefully) of the events handled
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if(notify_rx && (istat & UART0_LSR_RDR) ) vTaskNotifyGiveFromISR(notify_rx, hpw);
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if(notify_tx && (istat & UART0_LSR_THRE) ) vTaskNotifyGiveFromISR(notify_tx, hpw);
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if(on_receive && (istat & UART0_LSR_RDR) ) on_receive();
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}
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LpcDebugUart::LpcDebugUart(const LpcDebugUartConfig &cfg) {
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uart = nullptr; // set default value before checking which UART to configure
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if(cfg.pUART == LPC_USART0) {
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if(u0) return; // already exists
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else u0 = this;
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irqn = USART0_IRQn;
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}
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else {
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return;
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}
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uart = cfg.pUART; // set the actual value after validity checking
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if(cfg.tx.port >= 0) {
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Chip_IOCON_PinMuxSet(LPC_IOCON, cfg.tx.port, cfg.tx.pin, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN));
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}
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if(cfg.rx.port >= 0) {
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Chip_IOCON_PinMuxSet(LPC_IOCON, cfg.rx.port, cfg.rx.pin, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN));
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}
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notify_rx = nullptr;
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notify_tx = nullptr;
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on_receive = nullptr;
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/* Setup UART */
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Chip_UART0_Init(uart);
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Chip_UART0_SetBaud(LPC_USART0, cfg.speed);
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Chip_UART0_ConfigData(LPC_USART0, cfg.data);
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Chip_UART0_SetupFIFOS(LPC_USART0, (UART0_FCR_FIFO_EN | UART0_FCR_TRG_LEV2));
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Chip_UART0_TXEnable(uart);
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/* Before using the ring buffers, initialize them using the ring
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buffer init function */
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RingBuffer_Init(&rxring, rxbuff, 1, UART_RB_SIZE);
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RingBuffer_Init(&txring, txbuff, 1, UART_RB_SIZE);
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/* Enable receive data and line status interrupt */
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Chip_UART0_IntEnable(uart, UART0_IER_RBRINT | UART0_IER_RLSINT);
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NVIC_SetPriority(irqn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY + 1);
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/* Enable UART interrupt */
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NVIC_EnableIRQ(irqn);
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}
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LpcDebugUart::~LpcDebugUart() {
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if(uart != nullptr) {
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NVIC_DisableIRQ(irqn);
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Chip_UART0_IntDisable(uart, UART0_IER_RBRINT | UART0_IER_RLSINT);
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if(uart == LPC_USART0) {
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u0 = nullptr;
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}
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}
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}
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void LpcDebugUart::set_on_receive(void(*cb)(void))
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{
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on_receive = cb;
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}
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int LpcDebugUart::free()
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{
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std::lock_guard<Fmutex> lock(write_mutex);
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return UART_RB_SIZE - RingBuffer_GetCount(&txring);
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}
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int LpcDebugUart::peek()
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{
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std::lock_guard<Fmutex> lock(read_mutex);
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return RingBuffer_GetCount(&rxring);
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}
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int LpcDebugUart::read(char &c)
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{
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return read(&c, 1);
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}
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int LpcDebugUart::read(char *buffer, int len)
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{
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std::lock_guard<Fmutex> lock(read_mutex);
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if(RingBuffer_GetCount(&rxring) <= 0) {
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notify_rx = xTaskGetCurrentTaskHandle();
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while(RingBuffer_GetCount(&rxring) <= 0) {
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ulTaskNotifyTake( pdTRUE, portMAX_DELAY );
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}
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notify_rx = nullptr;
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}
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return Chip_UART0_ReadRB(uart, &rxring, buffer, len);
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}
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int LpcDebugUart::read(char *buffer, int len, TickType_t total_timeout, TickType_t ic_timeout)
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{
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std::lock_guard<Fmutex> lock(read_mutex);
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// we can't read more than ring buffer size at a time
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if(len > UART_RB_SIZE) len = UART_RB_SIZE;
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TimeOut_t timeoutState;
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vTaskSetTimeOutState(&timeoutState);
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notify_rx = xTaskGetCurrentTaskHandle();
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while(RingBuffer_GetCount(&rxring) < len && xTaskCheckForTimeOut(&timeoutState, &total_timeout) == pdFALSE) {
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TickType_t timeout = total_timeout > ic_timeout ? ic_timeout : total_timeout;
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if(ulTaskNotifyTake( pdTRUE, timeout ) == 0) break;
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}
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notify_rx = nullptr;
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return Chip_UART0_ReadRB(uart, &rxring, buffer, len);;
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}
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int LpcDebugUart::write(char c)
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{
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return write(&c, 1);
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}
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int LpcDebugUart::write(const char *s)
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{
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return write(s, strlen(s));
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}
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int LpcDebugUart::write(const char *buffer, int len)
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{
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std::lock_guard<Fmutex> lock(write_mutex);
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int pos = 0;
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notify_tx = xTaskGetCurrentTaskHandle();
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while(len > pos) {
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// restrict single write to ring buffer size
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int size = (len - pos) > UART_RB_SIZE ? UART_RB_SIZE : (len - pos);
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// wait until we have space in the ring buffer
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while(UART_RB_SIZE - RingBuffer_GetCount(&txring) < size) {
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ulTaskNotifyTake( pdTRUE, portMAX_DELAY );
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}
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pos += Chip_UART0_SendRB(uart, &txring, buffer+pos, size);
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}
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notify_tx = nullptr;
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return pos;
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}
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void LpcDebugUart::txbreak(bool brk)
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{
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// break handling not implemented yet
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}
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bool LpcDebugUart::rxbreak()
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{
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// break handling not implemented yet
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return false;
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}
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void LpcDebugUart::speed(int bps)
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{
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std::lock_guard<Fmutex> lockw(write_mutex);
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std::lock_guard<Fmutex> lockr(read_mutex);
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Chip_UART0_SetBaud(uart, bps);
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}
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bool LpcDebugUart::txempty()
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{
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std::lock_guard<Fmutex> lock(write_mutex);
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return (RingBuffer_GetCount(&txring) == 0);
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}
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63
source/shoh/src/peripherals/LpcDebugUart.h
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63
source/shoh/src/peripherals/LpcDebugUart.h
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@ -0,0 +1,63 @@
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/*
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* LpcDebugUart.h
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*
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* Created on: 6.5.2023
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*/
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#ifndef LPCDEBUGUART_H_
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#define LPCDEBUGUART_H_
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#include "chip.h"
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#include "FreeRTOS.h"
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#include "task.h"
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#include "semphr.h"
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#include "Fmutex.h"
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#include "LpcUart.h"
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struct LpcDebugUartConfig {
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LPC_USART0_T *pUART;
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uint32_t speed;
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uint32_t data;
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LpcPinMap tx;
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LpcPinMap rx;
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};
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class LpcDebugUart {
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public:
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LpcDebugUart(const LpcDebugUartConfig &cfg);
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LpcDebugUart(const LpcDebugUart &) = delete;
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virtual ~LpcDebugUart();
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int free(); /* get amount of free space in transmit buffer */
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int peek(); /* get number of received characters in receive buffer */
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int write(char c);
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int write(const char *s);
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int write(const char *buffer, int len);
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int read(char &c); /* get a single character. Returns number of characters read --> returns 0 if no character is available */
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int read(char *buffer, int len);
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int read(char *buffer, int len, TickType_t total_timeout, TickType_t ic_timeout = portMAX_DELAY);
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void txbreak(bool brk); /* set break signal on */
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bool rxbreak(); /* check if break is received */
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void speed(int bps); /* change transmission speed */
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bool txempty();
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void set_on_receive(void(*cb)(void));
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void isr(portBASE_TYPE *hpw); /* ISR handler. This will be called by the HW ISR handler. Do not call from application */
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private:
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LPC_USART0_T *uart;
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IRQn_Type irqn;
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/* currently we support only fixed size ring buffers */
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static const int UART_RB_SIZE = 128;
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/* Transmit and receive ring buffers */
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RINGBUFF_T txring;
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RINGBUFF_T rxring;
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uint8_t rxbuff[UART_RB_SIZE];
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uint8_t txbuff[UART_RB_SIZE];
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TaskHandle_t notify_rx;
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TaskHandle_t notify_tx;
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void (*on_receive)(void); // callback for received data notifications
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Fmutex read_mutex;
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Fmutex write_mutex;
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};
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#endif /* LPCUART_H_ */
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@ -9,32 +9,31 @@
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#include <mutex>
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#include "LpcUart.h"
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// Remove this when code will be reworked.
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#ifndef LPCUART_NOT_FIXED
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// Remove this when code will be reworked.
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/* shoh: Important differences
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* We don't have movable pins -> not needed.
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*
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* Muxing is like this:
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* Chip_IOCON_PinMuxSet(LPC_IOCON, 0, 14, (IOCON_FUNC4 | IOCON_MODE_INACT | IOCON_DIGMODE_EN));
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* Chip_IOCON_PinMuxSet(LPC_IOCON, 0, 13, (IOCON_FUNC4 | IOCON_MODE_INACT | IOCON_DIGMODE_EN));
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*
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* USART0 (the only debug uart):
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* Chip_IOCON_PinMuxSet(LPC_IOCON, 0, 18, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN));
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* Chip_IOCON_PinMuxSet(LPC_IOCON, 0, 19, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN));
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*/
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static LpcUart *u0;
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static LpcUart *u1;
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static LpcUart *u2;
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static LpcUart *u3;
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static LpcUart *u4;
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extern "C" {
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/**
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* @brief UART interrupt handler using ring buffers
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* @par shoh: Unlike in lpc15xx, lpc11u68 has shared interrupts for 1 and 4, 2 and 3.
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* shoh: Not sure how exactly it should be handled. UART0 is completely different compared to 1-4.
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* @return Nothing
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*/
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void UART0_IRQHandler(void)
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{
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portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
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if(u0) {
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u0->isr(&xHigherPriorityTaskWoken);
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}
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portEND_SWITCHING_ISR(xHigherPriorityTaskWoken);
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}
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void UART1_IRQHandler(void)
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void USART1_4_IRQHandler(void)
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{
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portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
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@ -42,10 +41,14 @@ void UART1_IRQHandler(void)
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u1->isr(&xHigherPriorityTaskWoken);
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}
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if(u4) {
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u4->isr(&xHigherPriorityTaskWoken);
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}
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portEND_SWITCHING_ISR(xHigherPriorityTaskWoken);
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}
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void UART2_IRQHandler(void)
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void USART2_3_IRQHandler(void)
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{
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portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
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@ -53,6 +56,10 @@ void UART2_IRQHandler(void)
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u2->isr(&xHigherPriorityTaskWoken);
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}
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if(u3) {
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u3->isr(&xHigherPriorityTaskWoken);
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}
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||||
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portEND_SWITCHING_ISR(xHigherPriorityTaskWoken);
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}
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@ -61,26 +68,23 @@ void UART2_IRQHandler(void)
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void LpcUart::isr(portBASE_TYPE *hpw) {
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// get interrupt status for notifications
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uint32_t istat = Chip_UART_GetIntStatus(uart);
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uint32_t istat = Chip_UARTN_GetIntStatus(uart);
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// chip library is used to handle receive and transmit
|
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Chip_UART_IRQRBHandler(uart, &rxring, &txring);
|
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Chip_UARTN_IRQRBHandler(uart, &rxring, &txring);
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|
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// notify of the events handled
|
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if(notify_rx && (istat & UART_STAT_RXRDY) ) vTaskNotifyGiveFromISR(notify_rx, hpw);
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if(notify_tx && (istat & UART_STAT_TXRDY) ) vTaskNotifyGiveFromISR(notify_tx, hpw);
|
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if(on_receive && (istat & UART_STAT_RXRDY) ) on_receive();
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if(notify_rx && (istat & UARTN_STAT_RXRDY) ) vTaskNotifyGiveFromISR(notify_rx, hpw);
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if(notify_tx && (istat & UARTN_STAT_TXRDY) ) vTaskNotifyGiveFromISR(notify_tx, hpw);
|
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if(on_receive && (istat & UARTN_STAT_RXRDY) ) on_receive();
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}
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||||
|
||||
bool LpcUart::init = false;
|
||||
|
||||
LpcUart::LpcUart(const LpcUartConfig &cfg) {
|
||||
CHIP_SWM_PIN_MOVABLE_T tx;
|
||||
CHIP_SWM_PIN_MOVABLE_T rx;
|
||||
CHIP_SWM_PIN_MOVABLE_T cts;
|
||||
CHIP_SWM_PIN_MOVABLE_T rts;
|
||||
bool use_rts = (cfg.rts.port >= 0);
|
||||
bool use_cts = (cfg.cts.port >= 0);
|
||||
//shoh: removed handshakes and movable pins.
|
||||
bool use_rts = false; //(cfg.rts.port >= 0);
|
||||
bool use_cts = false; //(cfg.cts.port >= 0);
|
||||
|
||||
if(!init) {
|
||||
init = true;
|
||||
@ -90,37 +94,30 @@ LpcUart::LpcUart(const LpcUartConfig &cfg) {
|
||||
* UARTs.
|
||||
* */
|
||||
/* Use main clock rate as base for UART baud rate divider */
|
||||
Chip_Clock_SetUARTBaseClockRate(Chip_Clock_GetMainClockRate(), false);
|
||||
Chip_Clock_SetUSARTNBaseClockRate(Chip_Clock_GetMainClockRate(), false); //(115200 * 256), false);
|
||||
}
|
||||
|
||||
uart = nullptr; // set default value before checking which UART to configure
|
||||
|
||||
if(cfg.pUART == LPC_USART0) {
|
||||
if(u0) return; // already exists
|
||||
else u0 = this;
|
||||
tx = SWM_UART0_TXD_O;
|
||||
rx = SWM_UART0_RXD_I;
|
||||
rts = SWM_UART0_RTS_O;
|
||||
cts = SWM_UART0_CTS_I;
|
||||
irqn = UART0_IRQn;
|
||||
}
|
||||
else if(cfg.pUART == LPC_USART1) {
|
||||
if(cfg.pUART == LPC_USART1) {
|
||||
if(u1) return; // already exists
|
||||
else u1 = this;
|
||||
tx = SWM_UART1_TXD_O;
|
||||
rx = SWM_UART1_RXD_I;
|
||||
rts = SWM_UART1_RTS_O;
|
||||
cts = SWM_UART1_CTS_I;
|
||||
irqn = UART1_IRQn;
|
||||
irqn = USART1_4_IRQn; //Shares interrupt with 4
|
||||
}
|
||||
else if(cfg.pUART == LPC_USART2) {
|
||||
if(u2) return; // already exists
|
||||
else u2 = this;
|
||||
tx = SWM_UART2_TXD_O;
|
||||
rx = SWM_UART2_RXD_I;
|
||||
use_rts = false; // UART2 does not support handshakes
|
||||
use_cts = false;
|
||||
irqn = UART2_IRQn;
|
||||
irqn = USART2_3_IRQn; //Shares interrupt with 3
|
||||
}
|
||||
else if(cfg.pUART == LPC_USART3) {
|
||||
if(u3) return; // already exists
|
||||
else u3 = this;
|
||||
irqn = USART2_3_IRQn;
|
||||
}
|
||||
else if(cfg.pUART == LPC_USART4) {
|
||||
if(u4) return; // already exists
|
||||
else u4 = this;
|
||||
irqn = USART1_4_IRQn;
|
||||
}
|
||||
else {
|
||||
return;
|
||||
@ -130,32 +127,28 @@ LpcUart::LpcUart(const LpcUartConfig &cfg) {
|
||||
|
||||
|
||||
if(cfg.tx.port >= 0) {
|
||||
Chip_IOCON_PinMuxSet(LPC_IOCON, cfg.tx.port, cfg.tx.pin, (IOCON_MODE_INACT | IOCON_DIGMODE_EN));
|
||||
Chip_SWM_MovablePortPinAssign(tx, cfg.tx.port, cfg.tx.pin);
|
||||
Chip_IOCON_PinMuxSet(LPC_IOCON, cfg.tx.port, cfg.tx.pin, (IOCON_FUNC4 | IOCON_MODE_INACT | IOCON_DIGMODE_EN));
|
||||
}
|
||||
|
||||
if(cfg.rx.port >= 0) {
|
||||
Chip_IOCON_PinMuxSet(LPC_IOCON, cfg.rx.port, cfg.rx.pin, (IOCON_MODE_INACT | IOCON_DIGMODE_EN));
|
||||
Chip_SWM_MovablePortPinAssign(rx, cfg.rx.port, cfg.rx.pin);
|
||||
Chip_IOCON_PinMuxSet(LPC_IOCON, cfg.rx.port, cfg.rx.pin, (IOCON_FUNC4 | IOCON_MODE_INACT | IOCON_DIGMODE_EN));
|
||||
}
|
||||
|
||||
if(use_cts) {
|
||||
Chip_IOCON_PinMuxSet(LPC_IOCON, cfg.cts.port, cfg.cts.pin, (IOCON_MODE_INACT | IOCON_DIGMODE_EN));
|
||||
Chip_SWM_MovablePortPinAssign(cts, cfg.cts.port, cfg.cts.pin);
|
||||
Chip_IOCON_PinMuxSet(LPC_IOCON, cfg.cts.port, cfg.cts.pin, (IOCON_FUNC4 | IOCON_MODE_INACT | IOCON_DIGMODE_EN));
|
||||
}
|
||||
|
||||
if(use_rts) {
|
||||
Chip_IOCON_PinMuxSet(LPC_IOCON, cfg.rts.port, cfg.rts.pin, (IOCON_MODE_INACT | IOCON_DIGMODE_EN));
|
||||
Chip_SWM_MovablePortPinAssign(rts, cfg.rts.port, cfg.rts.pin);
|
||||
Chip_IOCON_PinMuxSet(LPC_IOCON, cfg.rts.port, cfg.rts.pin, (IOCON_FUNC4 | IOCON_MODE_INACT | IOCON_DIGMODE_EN));
|
||||
}
|
||||
|
||||
notify_rx = nullptr;
|
||||
notify_tx = nullptr;
|
||||
on_receive = nullptr;
|
||||
/* Setup UART */
|
||||
Chip_UART_Init(uart);
|
||||
Chip_UART_ConfigData(uart, cfg.data);
|
||||
Chip_UART_SetBaud(uart, cfg.speed);
|
||||
Chip_UARTN_Init(uart);
|
||||
Chip_UARTN_ConfigData(uart, cfg.data);
|
||||
Chip_UARTN_SetBaud(uart, cfg.speed);
|
||||
|
||||
if(use_rts && cfg.rs485) {
|
||||
uart->CFG |= (1 << 20); // enable rs485 mode
|
||||
@ -163,8 +156,8 @@ LpcUart::LpcUart(const LpcUartConfig &cfg) {
|
||||
uart->CFG |= (1 << 21);// driver enable polarity (active high)
|
||||
}
|
||||
|
||||
Chip_UART_Enable(uart);
|
||||
Chip_UART_TXEnable(uart);
|
||||
Chip_UARTN_Enable(uart);
|
||||
Chip_UARTN_TXEnable(uart);
|
||||
|
||||
/* Before using the ring buffers, initialize them using the ring
|
||||
buffer init function */
|
||||
@ -173,8 +166,8 @@ LpcUart::LpcUart(const LpcUartConfig &cfg) {
|
||||
|
||||
|
||||
/* Enable receive data and line status interrupt */
|
||||
Chip_UART_IntEnable(uart, UART_INTEN_RXRDY);
|
||||
Chip_UART_IntDisable(uart, UART_INTEN_TXRDY); /* May not be needed */
|
||||
Chip_UARTN_IntEnable(uart, UARTN_INTEN_RXRDY);
|
||||
Chip_UARTN_IntDisable(uart, UARTN_INTEN_TXRDY); /* May not be needed */
|
||||
|
||||
NVIC_SetPriority(irqn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY + 1);
|
||||
/* Enable UART interrupt */
|
||||
@ -184,18 +177,21 @@ LpcUart::LpcUart(const LpcUartConfig &cfg) {
|
||||
LpcUart::~LpcUart() {
|
||||
if(uart != nullptr) {
|
||||
NVIC_DisableIRQ(irqn);
|
||||
Chip_UART_IntDisable(uart, UART_INTEN_RXRDY);
|
||||
Chip_UART_IntDisable(uart, UART_INTEN_TXRDY);
|
||||
Chip_UARTN_IntDisable(uart, UARTN_INTEN_RXRDY);
|
||||
Chip_UARTN_IntDisable(uart, UARTN_INTEN_TXRDY);
|
||||
|
||||
if(uart == LPC_USART0) {
|
||||
u0 = nullptr;
|
||||
}
|
||||
else if(uart == LPC_USART1) {
|
||||
if(uart == LPC_USART1) {
|
||||
u1 = nullptr;
|
||||
}
|
||||
else if(uart == LPC_USART2) {
|
||||
u2 = nullptr;
|
||||
}
|
||||
else if(uart == LPC_USART3) {
|
||||
u3 = nullptr;
|
||||
}
|
||||
else if(uart == LPC_USART4) {
|
||||
u4 = nullptr;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -236,7 +232,7 @@ int LpcUart::read(char *buffer, int len)
|
||||
notify_rx = nullptr;
|
||||
}
|
||||
|
||||
return Chip_UART_ReadRB(uart, &rxring, buffer, len);
|
||||
return Chip_UARTN_ReadRB(uart, &rxring, buffer, len);
|
||||
}
|
||||
|
||||
|
||||
@ -257,7 +253,7 @@ int LpcUart::read(char *buffer, int len, TickType_t total_timeout, TickType_t i
|
||||
}
|
||||
notify_rx = nullptr;
|
||||
|
||||
return Chip_UART_ReadRB(uart, &rxring, buffer, len);;
|
||||
return Chip_UARTN_ReadRB(uart, &rxring, buffer, len);;
|
||||
}
|
||||
|
||||
int LpcUart::write(char c)
|
||||
@ -285,7 +281,7 @@ int LpcUart::write(const char *buffer, int len)
|
||||
while(UART_RB_SIZE - RingBuffer_GetCount(&txring) < size) {
|
||||
ulTaskNotifyTake( pdTRUE, portMAX_DELAY );
|
||||
}
|
||||
pos += Chip_UART_SendRB(uart, &txring, buffer+pos, size);
|
||||
pos += Chip_UARTN_SendRB(uart, &txring, buffer+pos, size);
|
||||
}
|
||||
notify_tx = nullptr;
|
||||
|
||||
@ -308,7 +304,7 @@ void LpcUart::speed(int bps)
|
||||
std::lock_guard<Fmutex> lockw(write_mutex);
|
||||
std::lock_guard<Fmutex> lockr(read_mutex);
|
||||
|
||||
Chip_UART_SetBaud(uart, bps);
|
||||
Chip_UARTN_SetBaud(uart, bps);
|
||||
}
|
||||
|
||||
bool LpcUart::txempty()
|
||||
@ -317,7 +313,3 @@ bool LpcUart::txempty()
|
||||
|
||||
return (RingBuffer_GetCount(&txring) == 0);
|
||||
}
|
||||
|
||||
// Remove this when code will be reworked.
|
||||
#endif /* LPCUART_NOT_FIXED */
|
||||
// Remove this when code will be reworked.
|
||||
|
||||
@ -8,12 +8,6 @@
|
||||
#ifndef LPCUART_H_
|
||||
#define LPCUART_H_
|
||||
|
||||
// Remove this when code will be reworked.
|
||||
#define LPCUART_NOT_FIXED
|
||||
#ifndef LPCUART_NOT_FIXED
|
||||
// Remove this when code will be reworked.
|
||||
|
||||
|
||||
#include "chip.h"
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
@ -26,13 +20,13 @@ struct LpcPinMap {
|
||||
};
|
||||
|
||||
struct LpcUartConfig {
|
||||
LPC_USART_T *pUART;
|
||||
LPC_USARTN_T *pUART;
|
||||
uint32_t speed;
|
||||
uint32_t data;
|
||||
bool rs485;
|
||||
LpcPinMap tx;
|
||||
LpcPinMap rx;
|
||||
LpcPinMap rts; /* used as output enable if RS-485 mode is enabled */
|
||||
LpcPinMap rts; /* used as output enable if RS-485 mode is enabled */ //shoh: Psst. Actually, not used anywhere.
|
||||
LpcPinMap cts;
|
||||
};
|
||||
|
||||
@ -58,7 +52,7 @@ public:
|
||||
|
||||
void isr(portBASE_TYPE *hpw); /* ISR handler. This will be called by the HW ISR handler. Do not call from application */
|
||||
private:
|
||||
LPC_USART_T *uart;
|
||||
LPC_USARTN_T *uart;
|
||||
IRQn_Type irqn;
|
||||
/* currently we support only fixed size ring buffers */
|
||||
static const int UART_RB_SIZE = 128;
|
||||
@ -75,8 +69,4 @@ private:
|
||||
Fmutex write_mutex;
|
||||
};
|
||||
|
||||
// Remove this when code will be reworked.
|
||||
#endif /* LPCUART_NOT_FIXED */
|
||||
// Remove this when code will be reworked.
|
||||
|
||||
#endif /* LPCUART_H_ */
|
||||
|
||||
91
source/shoh/src/peripherals/retarget_uart.cpp
Normal file
91
source/shoh/src/peripherals/retarget_uart.cpp
Normal file
@ -0,0 +1,91 @@
|
||||
/*
|
||||
* retarget_uart.cpp
|
||||
*
|
||||
* Created on: 28.9.2021
|
||||
* Author: keijo
|
||||
*/
|
||||
|
||||
#include "LpcDebugUart.h"
|
||||
|
||||
static LpcDebugUart *dbgu;
|
||||
|
||||
void retarget_init()
|
||||
{
|
||||
LpcPinMap none = {-1, -1}; // unused pin has negative values in it
|
||||
//Sadly, it seems that only USART0 is redirected to USB.
|
||||
//It means that those are pins PIO0_18 and PIO0_19
|
||||
LpcPinMap txpin = { 0, 19 }; // transmit pin that goes to debugger's UART->USB converter
|
||||
LpcPinMap rxpin = { 0, 18 }; // receive pin that goes to debugger's UART->USB converter
|
||||
LpcDebugUartConfig cfg = { LPC_USART0, 115200, (UART0_LCR_WLEN8 | UART0_LCR_SBS_1BIT), txpin, rxpin };
|
||||
dbgu = new LpcDebugUart(cfg);
|
||||
}
|
||||
|
||||
extern "C" {
|
||||
|
||||
// ******************************************************************
|
||||
// Redlib C Library function : __sys_write
|
||||
// Newlib C library function : _write
|
||||
//
|
||||
// Function called by bottom level of printf routine within C library.
|
||||
// With the default semihosting stub, this would write the
|
||||
// character(s) to the debugger console window (which acts as
|
||||
// stdout). But this version writes the character(s) to UART
|
||||
// ******************************************************************
|
||||
#if defined (__REDLIB__)
|
||||
int __sys_write(int iFileHandle, char *pcBuffer, int iLength) {
|
||||
#elif defined (__NEWLIB__)
|
||||
int _write(int iFileHandle, char *pcBuffer, int iLength) {
|
||||
#endif
|
||||
if(dbgu) {
|
||||
int len = iLength;
|
||||
while(len > 0) {
|
||||
if(*pcBuffer == '\n') { // send a CR before every LF
|
||||
while(dbgu->write('\r')==0);
|
||||
}
|
||||
while(dbgu->write(*pcBuffer)==0);
|
||||
++pcBuffer;
|
||||
--len;
|
||||
}
|
||||
}
|
||||
// Function returns number of bytes written
|
||||
return iLength;
|
||||
}
|
||||
|
||||
#if defined (__REDLIB__)
|
||||
// ******************************************************************
|
||||
// Redlib C Library function : __sys_readc
|
||||
//
|
||||
// Called by bottom level of scanf routine within RedLib C library
|
||||
// to read a character. With the default semihosting stub, this
|
||||
// would read the character from the debugger console window (which
|
||||
// acts as stdin). But this version reads the character from UART
|
||||
// ******************************************************************
|
||||
|
||||
int __sys_readc(void) {
|
||||
char c;
|
||||
if(dbgu && dbgu->read(c)) return c;
|
||||
else return -1;
|
||||
|
||||
}
|
||||
// #endif REDLIB __sys_readc()
|
||||
|
||||
#elif defined (__NEWLIB__)
|
||||
// ******************************************************************
|
||||
// Function _read
|
||||
//
|
||||
// Called by bottom level of scanf routine within Newlib C library
|
||||
// to read multiple characters. With the default semihosting stub, this
|
||||
// would read characters from the debugger console window (which
|
||||
// acts as stdin). But this version reads the characters from UART
|
||||
// ******************************************************************
|
||||
int _read(int iFileHandle, char *pcBuffer, int iLength) {
|
||||
|
||||
// TODO : Should potentially check that iFileHandle == 0 to confirm
|
||||
// that read is from stdin
|
||||
if(!dbgu) return 0;
|
||||
return dbgu->read(pcBuffer, iLength);
|
||||
}
|
||||
|
||||
#endif // NEWLIB _read()
|
||||
|
||||
}
|
||||
14
source/shoh/src/peripherals/retarget_uart.h
Normal file
14
source/shoh/src/peripherals/retarget_uart.h
Normal file
@ -0,0 +1,14 @@
|
||||
/*
|
||||
* retarget_uart.h
|
||||
*
|
||||
* Created on: 28.9.2021
|
||||
* Author: keijo
|
||||
*/
|
||||
|
||||
#ifndef RETARGET_UART_H_
|
||||
#define RETARGET_UART_H_
|
||||
|
||||
void retarget_init();
|
||||
|
||||
|
||||
#endif /* RETARGET_UART_H_ */
|
||||
@ -21,15 +21,19 @@ void Master::taskFunction() {
|
||||
{
|
||||
case ThreadCommon::RotaryAction::Right:
|
||||
Board_LED_Set(ThreadCommon::RotaryAction::Right, LedState);
|
||||
printf("Right\r\n");
|
||||
break;
|
||||
case ThreadCommon::RotaryAction::Left:
|
||||
Board_LED_Set(ThreadCommon::RotaryAction::Left, LedState);
|
||||
printf("Left\r\n");
|
||||
break;
|
||||
case ThreadCommon::RotaryAction::Press:
|
||||
Board_LED_Set(ThreadCommon::RotaryAction::Press, LedState);
|
||||
printf("Press\r\n");
|
||||
break;
|
||||
case ThreadCommon::RotaryAction::Idle:
|
||||
Board_LED_Set(ThreadCommon::RotaryAction::Right, LedState);
|
||||
printf("Idle\r\n");
|
||||
break;
|
||||
}
|
||||
LedState = !LedState;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user