314 lines
14 KiB
C
314 lines
14 KiB
C
/*
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* @brief LPC15xx I2C driver
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2014
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __I2C_COMMON_15XX_H_
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#define __I2C_COMMON_15XX_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup I2C_15XX CHIP: LPC15xx I2C driver
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* @ingroup CHIP_15XX_Drivers
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* @{
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*/
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/**
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* @brief I2C register block structure
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*/
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typedef struct { /* I2C0 Structure */
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__IO uint32_t CFG; /*!< I2C Configuration Register common for Master, Slave and Monitor */
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__IO uint32_t STAT; /*!< I2C Status Register common for Master, Slave and Monitor */
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__IO uint32_t INTENSET; /*!< I2C Interrupt Enable Set Register common for Master, Slave and Monitor */
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__O uint32_t INTENCLR; /*!< I2C Interrupt Enable Clear Register common for Master, Slave and Monitor */
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__IO uint32_t TIMEOUT; /*!< I2C Timeout value Register */
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__IO uint32_t CLKDIV; /*!< I2C Clock Divider Register */
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__I uint32_t INTSTAT; /*!< I2C Interrupt Status Register */
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__I uint32_t RESERVED0;
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__IO uint32_t MSTCTL; /*!< I2C Master Control Register */
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__IO uint32_t MSTTIME; /*!< I2C Master Time Register for SCL */
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__IO uint32_t MSTDAT; /*!< I2C Master Data Register */
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__I uint32_t RESERVED1[5];
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__IO uint32_t SLVCTL; /*!< I2C Slave Control Register */
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__IO uint32_t SLVDAT; /*!< I2C Slave Data Register */
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__IO uint32_t SLVADR[4]; /*!< I2C Slave Address Registers */
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__IO uint32_t SLVQUAL0; /*!< I2C Slave Address Qualifier 0 Register */
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__I uint32_t RESERVED2[9];
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__I uint32_t MONRXDAT; /*!< I2C Monitor Data Register */
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} LPC_I2C_T;
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/*
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* @brief I2C Configuration register Bit definition
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*/
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#define I2C_CFG_MSTEN (1 << 0) /*!< Master Enable/Disable Bit */
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#define I2C_CFG_SLVEN (1 << 1) /*!< Slave Enable/Disable Bit */
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#define I2C_CFG_MONEN (1 << 2) /*!< Monitor Enable/Disable Bit */
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#define I2C_CFG_TIMEOUTEN (1 << 3) /*!< Timeout Enable/Disable Bit */
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#define I2C_CFG_MONCLKSTR (1 << 4) /*!< Monitor Clock Stretching Bit */
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#define I2C_CFG_MASK ((uint32_t) 0x1F) /*!< Configuration register Mask */
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/*
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* @brief I2C Status register Bit definition
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*/
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#define I2C_STAT_MSTPENDING (1 << 0) /*!< Master Pending Status Bit */
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#define I2C_STAT_MSTSTATE (0x7 << 1) /*!< Master State Code */
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#define I2C_STAT_MSTRARBLOSS (1 << 4) /*!< Master Arbitration Loss Bit */
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#define I2C_STAT_MSTSTSTPERR (1 << 6) /*!< Master Start Stop Error Bit */
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#define I2C_STAT_SLVPENDING (1 << 8) /*!< Slave Pending Status Bit */
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#define I2C_STAT_SLVSTATE (0x3 << 9) /*!< Slave State Code */
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#define I2C_STAT_SLVNOTSTR (1 << 11) /*!< Slave not stretching Clock Bit */
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#define I2C_STAT_SLVIDX (0x3 << 12) /*!< Slave Address Index */
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#define I2C_STAT_SLVSEL (1 << 14) /*!< Slave Selected Bit */
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#define I2C_STAT_SLVDESEL (1 << 15) /*!< Slave Deselect Bit */
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#define I2C_STAT_MONRDY (1 << 16) /*!< Monitor Ready Bit */
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#define I2C_STAT_MONOV (1 << 17) /*!< Monitor Overflow Flag */
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#define I2C_STAT_MONACTIVE (1 << 18) /*!< Monitor Active Flag */
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#define I2C_STAT_MONIDLE (1 << 19) /*!< Monitor Idle Flag */
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#define I2C_STAT_EVENTTIMEOUT (1 << 24) /*!< Event Timeout Interrupt Flag */
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#define I2C_STAT_SCLTIMEOUT (1 << 25) /*!< SCL Timeout Interrupt Flag */
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#define I2C_STAT_MSTCODE_IDLE (0) /*!< Master Idle State Code */
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#define I2C_STAT_MSTCODE_RXREADY (1) /*!< Master Receive Ready State Code */
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#define I2C_STAT_MSTCODE_TXREADY (2) /*!< Master Transmit Ready State Code */
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#define I2C_STAT_MSTCODE_NACKADR (3) /*!< Master NACK by slave on address State Code */
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#define I2C_STAT_MSTCODE_NACKDAT (4) /*!< Master NACK by slave on data State Code */
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#define I2C_STAT_SLVCODE_ADDR (0) /*!< Master Idle State Code */
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#define I2C_STAT_SLVCODE_RX (1) /*!< Received data is available Code */
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#define I2C_STAT_SLVCODE_TX (2) /*!< Data can be transmitted Code */
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/*
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* @brief I2C Interrupt Enable Set register Bit definition
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*/
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#define I2C_INTENSET_MSTPENDING (1 << 0) /*!< Master Pending Interrupt Enable Bit */
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#define I2C_INTENSET_MSTRARBLOSS (1 << 4) /*!< Master Arbitration Loss Interrupt Enable Bit */
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#define I2C_INTENSET_MSTSTSTPERR (1 << 6) /*!< Master Start Stop Error Interrupt Enable Bit */
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#define I2C_INTENSET_SLVPENDING (1 << 8) /*!< Slave Pending Interrupt Enable Bit */
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#define I2C_INTENSET_SLVNOTSTR (1 << 11) /*!< Slave not stretching Clock Interrupt Enable Bit */
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#define I2C_INTENSET_SLVDESEL (1 << 15) /*!< Slave Deselect Interrupt Enable Bit */
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#define I2C_INTENSET_MONRDY (1 << 16) /*!< Monitor Ready Interrupt Enable Bit */
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#define I2C_INTENSET_MONOV (1 << 17) /*!< Monitor Overflow Interrupt Enable Bit */
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#define I2C_INTENSET_MONIDLE (1 << 19) /*!< Monitor Idle Interrupt Enable Bit */
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#define I2C_INTENSET_EVENTTIMEOUT (1 << 24) /*!< Event Timeout Interrupt Enable Bit */
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#define I2C_INTENSET_SCLTIMEOUT (1 << 25) /*!< SCL Timeout Interrupt Enable Bit */
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/*
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* @brief I2C Interrupt Enable Clear register Bit definition
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*/
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#define I2C_INTENCLR_MSTPENDING (1 << 0) /*!< Master Pending Interrupt Clear Bit */
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#define I2C_INTENCLR_MSTRARBLOSS (1 << 4) /*!< Master Arbitration Loss Interrupt Clear Bit */
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#define I2C_INTENCLR_MSTSTSTPERR (1 << 6) /*!< Master Start Stop Error Interrupt Clear Bit */
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#define I2C_INTENCLR_SLVPENDING (1 << 8) /*!< Slave Pending Interrupt Clear Bit */
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#define I2C_INTENCLR_SLVNOTSTR (1 << 11) /*!< Slave not stretching Clock Interrupt Clear Bit */
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#define I2C_INTENCLR_SLVDESEL (1 << 15) /*!< Slave Deselect Interrupt Clear Bit */
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#define I2C_INTENCLR_MONRDY (1 << 16) /*!< Monitor Ready Interrupt Clear Bit */
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#define I2C_INTENCLR_MONOV (1 << 17) /*!< Monitor Overflow Interrupt Clear Bit */
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#define I2C_INTENCLR_MONIDLE (1 << 19) /*!< Monitor Idle Interrupt Clear Bit */
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#define I2C_INTENCLR_EVENTTIMEOUT (1 << 24) /*!< Event Timeout Interrupt Clear Bit */
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#define I2C_INTENCLR_SCLTIMEOUT (1 << 25) /*!< SCL Timeout Interrupt Clear Bit */
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/*
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* @brief I2C TimeOut Value Macro
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*/
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#define I2C_TIMEOUT_VAL(n) (((uint32_t) ((n) - 1) & 0xFFF0) | 0x000F) /*!< Macro for Timeout value register */
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/*
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* @brief I2C Interrupt Status register Bit definition
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*/
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#define I2C_INTSTAT_MSTPENDING (1 << 0) /*!< Master Pending Interrupt Status Bit */
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#define I2C_INTSTAT_MSTRARBLOSS (1 << 4) /*!< Master Arbitration Loss Interrupt Status Bit */
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#define I2C_INTSTAT_MSTSTSTPERR (1 << 6) /*!< Master Start Stop Error Interrupt Status Bit */
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#define I2C_INTSTAT_SLVPENDING (1 << 8) /*!< Slave Pending Interrupt Status Bit */
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#define I2C_INTSTAT_SLVNOTSTR (1 << 11) /*!< Slave not stretching Clock Interrupt Status Bit */
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#define I2C_INTSTAT_SLVDESEL (1 << 15) /*!< Slave Deselect Interrupt Status Bit */
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#define I2C_INTSTAT_MONRDY (1 << 16) /*!< Monitor Ready Interrupt Status Bit */
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#define I2C_INTSTAT_MONOV (1 << 17) /*!< Monitor Overflow Interrupt Status Bit */
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#define I2C_INTSTAT_MONIDLE (1 << 19) /*!< Monitor Idle Interrupt Status Bit */
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#define I2C_INTSTAT_EVENTTIMEOUT (1 << 24) /*!< Event Timeout Interrupt Status Bit */
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#define I2C_INTSTAT_SCLTIMEOUT (1 << 25) /*!< SCL Timeout Interrupt Status Bit */
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/*
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* @brief I2C Master Control register Bit definition
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*/
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#define I2C_MSTCTL_MSTCONTINUE (1 << 0) /*!< Master Continue Bit */
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#define I2C_MSTCTL_MSTSTART (1 << 1) /*!< Master Start Control Bit */
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#define I2C_MSTCTL_MSTSTOP (1 << 2) /*!< Master Stop Control Bit */
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#define I2C_MSTCTL_MSTDMA (1 << 3) /*!< Master DMA Enable Bit */
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/*
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* @brief I2C Master Time Register Field definition
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*/
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#define I2C_MSTTIME_MSTSCLLOW (0x07 << 0) /*!< Master SCL Low Time field */
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#define I2C_MSTTIME_MSTSCLHIGH (0x07 << 4) /*!< Master SCL High Time field */
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/*
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* @brief I2C Master Data Mask
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*/
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#define I2C_MSTDAT_DATAMASK ((uint32_t) 0x00FF << 0) /*!< Master data mask */
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/*
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* @brief I2C Slave Control register Bit definition
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*/
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#define I2C_SLVCTL_SLVCONTINUE (1 << 0) /*!< Slave Continue Bit */
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#define I2C_SLVCTL_SLVNACK (1 << 1) /*!< Slave NACK Bit */
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#define I2C_SLVCTL_SLVDMA (1 << 3) /*!< Slave DMA Enable Bit */
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/*
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* @brief I2C Slave Data Mask
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*/
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#define I2C_SLVDAT_DATAMASK ((uint32_t) 0x00FF << 0) /*!< Slave data mask */
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/*
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* @brief I2C Slave Address register Bit definition
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*/
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#define I2C_SLVADR_SADISABLE (1 << 0) /*!< Slave Address n Disable Bit */
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#define I2C_SLVADR_SLVADR (0x7F << 1) /*!< Slave Address field */
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#define I2C_SLVADR_MASK ((uint32_t) 0x00FF) /*!< Slave Address Mask */
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/*
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* @brief I2C Slave Address Qualifier 0 Register Bit definition
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*/
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#define I2C_SLVQUAL_QUALMODE0 (1 << 0) /*!< Slave Qualifier Mode Enable Bit */
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#define I2C_SLVQUAL_SLVQUAL0 (0x7F << 1) /*!< Slave Qualifier Address for Address 0 */
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/*
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* @brief I2C Monitor Data Register Bit definition
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*/
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#define I2C_MONRXDAT_DATA (0xFF << 0) /*!< Monitor Function Receive Data Field */
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#define I2C_MONRXDAT_MONSTART (1 << 8) /*!< Monitor Received Start Bit */
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#define I2C_MONRXDAT_MONRESTART (1 << 9) /*!< Monitor Received Repeated Start Bit */
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#define I2C_MONRXDAT_MONNACK (1 << 10) /*!< Monitor Received Nack Bit */
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/**
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* @brief Initialize I2C Interface
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* @param pI2C : Pointer to selected I2C peripheral
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* @return Nothing
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* @note This function enables the I2C clock for both the master and
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* slave interfaces if the I2C channel.
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*/
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void Chip_I2C_Init(LPC_I2C_T *pI2C);
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/**
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* @brief Shutdown I2C Interface
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* @param pI2C : Pointer to selected I2C peripheral
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* @return Nothing
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* @note This function disables the I2C clock for both the master and
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* slave interfaces if the I2C channel.
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*/
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void Chip_I2C_DeInit(LPC_I2C_T *pI2C);
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/**
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* @brief Sets I2C Clock Divider registers
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* @param pI2C : Pointer to selected I2C peripheral
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* @param clkdiv : Clock Divider value for I2C, value is between (1 - 65536)
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* @return Nothing
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* @note The clock to I2C block is determined by the following formula (I2C_PCLK
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* is the frequency of the system clock): <br>
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* I2C Clock Frequency = (I2C_PCLK)/clkdiv;
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*/
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static INLINE void Chip_I2C_SetClockDiv(LPC_I2C_T *pI2C, uint32_t clkdiv)
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{
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if ((clkdiv >= 1) && (clkdiv <= 65536)) {
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pI2C->CLKDIV = clkdiv - 1;
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}
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else {
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pI2C->CLKDIV = 0;
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}
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}
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/**
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* @brief Get I2C Clock Divider registers
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* @param pI2C : Pointer to selected I2C peripheral
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* @return Clock Divider value
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* @note Return the divider value for the I2C block
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* It is the CLKDIV register value + 1
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*/
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static INLINE uint32_t Chip_I2C_GetClockDiv(LPC_I2C_T *pI2C)
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{
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return (pI2C->CLKDIV & 0xFFFF) + 1;
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}
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/**
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* @brief Enable I2C Interrupts
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* @param pI2C : Pointer to selected I2C peripheral
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* @param intEn : ORed Value of I2C_INTENSET_* values to enable
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* @return Nothing
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*/
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static INLINE void Chip_I2C_EnableInt(LPC_I2C_T *pI2C, uint32_t intEn)
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{
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pI2C->INTENSET = intEn;
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}
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/**
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* @brief Disable I2C Interrupts
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* @param pI2C : Pointer to selected I2C peripheral
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* @param intClr : ORed Value of I2C_INTENSET_* values to disable
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* @return Nothing
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*/
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static INLINE void Chip_I2C_DisableInt(LPC_I2C_T *pI2C, uint32_t intClr)
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{
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pI2C->INTENCLR = intClr;
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}
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/**
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* @brief Disable I2C Interrupts
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* @param pI2C : Pointer to selected I2C peripheral
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* @param intClr : ORed Value of I2C_INTENSET_* values to disable
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* @return Nothing
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* @note It is recommended to use the Chip_I2C_DisableInt() function
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* instead of this function.
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*/
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static INLINE void Chip_I2C_ClearInt(LPC_I2C_T *pI2C, uint32_t intClr)
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{
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Chip_I2C_DisableInt(pI2C, intClr);
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}
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/**
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* @brief Returns pending I2C Interrupts
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* @param pI2C : Pointer to selected I2C peripheral
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* @return All pending interrupts, mask with I2C_INTENSET_* to determine specific interrupts
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*/
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static INLINE uint32_t Chip_I2C_GetPendingInt(LPC_I2C_T *pI2C)
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{
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return pI2C->INTSTAT;
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}
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __I2C_COMMON_15XX_H_ */
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