693 lines
21 KiB
C
693 lines
21 KiB
C
/*
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* @brief LPC15XX Clock control functions
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2013
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __CLOCK_15XX_H_
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#define __CLOCK_15XX_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup CLOCK_15XX CHIP: LPC15xx Clock Control block driver
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* @ingroup CHIP_15XX_Drivers
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* @{
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*/
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/** Internal oscillator frequency */
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#define SYSCTL_IRC_FREQ (12000000)
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/** Internal watchdog oscillator frequency */
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#define SYSCTL_WDTOSC_FREQ (503000)
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/** @defgroup CLOCK_15XXcCHIP_SEL: Clock source selection functions
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* These functions provide selection of clocks for system functions such as
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* the USB clock, main system clock, or the clock output pin.
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* @{
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*/
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/**
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* Clock source selections for only the main A system clock. The main A system
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* clock is used as an input into the main B system clock selector. Main clock A
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* only needs to be setup if the main clock A input is used in the main clock
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* system selector.
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*/
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typedef enum CHIP_SYSCTL_MAIN_A_CLKSRC {
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SYSCTL_MAIN_A_CLKSRC_IRC = 0, /*!< Internal oscillator */
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SYSCTL_MAIN_A_CLKSRCA_MAINOSC, /*!< Crystal (main) oscillator in */
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SYSCTL_MAIN_A_CLKSRCA_SYSOSC = SYSCTL_MAIN_A_CLKSRCA_MAINOSC,
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SYSCTL_MAIN_A_CLKSRCA_WDTOSC, /*!< Watchdog oscillator rate */
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SYSCTL_MAIN_A_CLKSRCA_RESERVED,
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} CHIP_SYSCTL_MAIN_A_CLKSRC_T;
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/**
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* @brief Set main A system clock source
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* @param src : Clock source for main A
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* @return Nothing
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* @note This function only neesd to be setup if main clock A will be
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* selected in the Chip_Clock_GetMain_B_ClockRate() function.
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*/
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STATIC INLINE void Chip_Clock_SetMain_A_ClockSource(CHIP_SYSCTL_MAIN_A_CLKSRC_T src)
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{
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LPC_SYSCTL->MAINCLKSELA = (uint32_t) src;
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}
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/**
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* @brief Returns the main A clock source
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* @return Returns which clock is used for the main A
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*/
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STATIC INLINE CHIP_SYSCTL_MAIN_A_CLKSRC_T Chip_Clock_GetMain_A_ClockSource(void)
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{
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return (CHIP_SYSCTL_MAIN_A_CLKSRC_T) (LPC_SYSCTL->MAINCLKSELA);
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}
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/**
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* @brief Return main A clock rate
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* @return main A clock rate in Hz
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*/
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uint32_t Chip_Clock_GetMain_A_ClockRate(void);
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/**
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* Clock sources for only main B system clock
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*/
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typedef enum CHIP_SYSCTL_MAIN_B_CLKSRC {
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SYSCTL_MAIN_B_CLKSRC_MAINCLKSELA = 0, /*!< main clock A */
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SYSCTL_MAIN_B_CLKSRC_SYSPLLIN, /*!< System PLL input */
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SYSCTL_MAIN_B_CLKSRC_SYSPLLOUT, /*!< System PLL output */
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SYSCTL_MAIN_B_CLKSRC_RTC, /*!< RTC oscillator 32KHz output */
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} CHIP_SYSCTL_MAIN_B_CLKSRC_T;
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/**
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* @brief Set main B system clock source
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* @param src : Clock source for main B
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* @return Nothing
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*/
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STATIC INLINE void Chip_Clock_SetMain_B_ClockSource(CHIP_SYSCTL_MAIN_B_CLKSRC_T src)
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{
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LPC_SYSCTL->MAINCLKSELB = (uint32_t) src;
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}
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/**
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* @brief Returns the main B clock source
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* @return Returns which clock is used for the main B
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*/
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STATIC INLINE CHIP_SYSCTL_MAIN_B_CLKSRC_T Chip_Clock_GetMain_B_ClockSource(void)
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{
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return (CHIP_SYSCTL_MAIN_B_CLKSRC_T) (LPC_SYSCTL->MAINCLKSELB);
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}
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/**
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* @brief Return main B clock rate
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* @return main B clock rate
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*/
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uint32_t Chip_Clock_GetMain_B_ClockRate(void);
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/**
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* Clock sources for main system clock. This is a mix of both main clock A
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* and B seelctions.
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*/
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typedef enum CHIP_SYSCTL_MAINCLKSRC {
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SYSCTL_MAINCLKSRC_IRC = 0, /*!< Internal oscillator */
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SYSCTL_MAINCLKSRCA_MAINOSC, /*!< Crystal (main) oscillator in */
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SYSCTL_MAINCLKSRCA_SYSOSC = SYSCTL_MAINCLKSRCA_MAINOSC,
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SYSCTL_MAINCLKSRCA_WDTOSC, /*!< Watchdog oscillator rate */
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SYSCTL_MAINCLKSRC_SYSPLLIN = 5, /*!< System PLL input */
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SYSCTL_MAINCLKSRC_SYSPLLOUT, /*!< System PLL output */
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SYSCTL_MAINCLKSRC_RTC, /*!< RTC oscillator 32KHz output */
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} CHIP_SYSCTL_MAINCLKSRC_T;
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/**
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* @brief Set main system clock source
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* @param src : Main clock source
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* @return Nothing
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* @note This functions handles setup of both A and B main clock sources.
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*/
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void Chip_Clock_SetMainClockSource(CHIP_SYSCTL_MAINCLKSRC_T src);
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/**
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* @brief Returns the main clock source
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* @return Returns which clock is used for the main clock source
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* @note This functions handles both A and B main clock sources.
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*/
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CHIP_SYSCTL_MAINCLKSRC_T Chip_Clock_GetMainClockSource(void);
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/**
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* @brief Return main clock rate
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* @return main clock rate
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*/
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uint32_t Chip_Clock_GetMainClockRate(void);
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/**
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* @brief Return system clock rate
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* @return system clock rate
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*/
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uint32_t Chip_Clock_GetSystemClockRate(void);
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/**
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* Clock sources for USB (usb_clk)
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*/
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typedef enum CHIP_SYSCTL_USBCLKSRC {
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SYSCTL_USBCLKSRC_IRC = 0, /*!< Internal oscillator */
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SYSCTL_USBCLKSRC_MAINOSC, /*!< Crystal (main) oscillator in */
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SYSCTL_USBCLKSRC_SYSOSC = SYSCTL_USBCLKSRC_MAINOSC,
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SYSCTL_USBCLKSRC_PLLOUT, /*!< USB PLL out */
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SYSCTL_USBCLKSRC_MAINSYSCLK, /*!< Main system clock (B) */
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} CHIP_SYSCTL_USBCLKSRC_T;
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/**
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* @brief Set USB clock source and divider
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* @param src : Clock source for USB
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* @param div : divider for USB clock
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* @return Nothing
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* @note Use 0 to disable, or a divider value of 1 to 255. The USB clock
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* rate is either the main system clock or USB PLL output clock divided
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* by this value. This function will also toggle the clock source
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* update register to update the clock source.
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*/
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STATIC INLINE void Chip_Clock_SetUSBClockSource(CHIP_SYSCTL_USBCLKSRC_T src, uint32_t div)
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{
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LPC_SYSCTL->USBCLKSEL = (uint32_t) src;
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LPC_SYSCTL->USBCLKDIV = div;
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}
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/**
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* Clock sources for ADC asynchronous clock source select
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*/
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typedef enum CHIP_SYSCTL_ADCASYNCCLKSRC {
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SYSCTL_ADCASYNCCLKSRC_IRC = 0, /*!< Internal oscillator */
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SYSCTL_ADCASYNCCLKSRC_SYSPLLOUT, /*!< System PLL out */
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SYSCTL_ADCASYNCCLKSRC_USBPLLOUT, /*!< USB PLL out */
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SYSCTL_ADCASYNCCLKSRC_SCTPLLOUT /*!< SCT PLL out */
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} CHIP_SYSCTL_ADCASYNCCLKSRC_T;
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/**
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* @brief Set the ADC asynchronous clock source
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* @param src : ADC asynchronous clock source
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* @return Nothing
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*/
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STATIC INLINE void Chip_Clock_SetADCASYNCSource(CHIP_SYSCTL_ADCASYNCCLKSRC_T src)
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{
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LPC_SYSCTL->ADCASYNCCLKSEL = (uint32_t) src;
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}
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/**
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* @brief Returns the ADC asynchronous clock source
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* @return Returns which clock is used for the ADC asynchronous clock source
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*/
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STATIC INLINE CHIP_SYSCTL_ADCASYNCCLKSRC_T Chip_Clock_GetADCASYNCSource(void)
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{
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return (CHIP_SYSCTL_ADCASYNCCLKSRC_T) (LPC_SYSCTL->ADCASYNCCLKSEL);
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}
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/**
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* @brief Return ADC asynchronous clock rate
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* @return ADC asynchronous clock rate (not including divider)
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*/
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uint32_t Chip_Clock_GetADCASYNCRate(void);
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/**
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* Clock sources for CLKOUT
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*/
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typedef enum CHIP_SYSCTL_CLKOUTSRC {
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SYSCTL_CLKOUTSRC_IRC = 0, /*!< Internal oscillator for CLKOUT */
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SYSCTL_CLKOUTSRC_MAINOSC, /*!< Main oscillator for CLKOUT */
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SYSCTL_CLKOUTSRC_SYSOSC = SYSCTL_CLKOUTSRC_MAINOSC,
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SYSCTL_CLKOUTSRC_WDTOSC, /*!< Watchdog oscillator for CLKOUT */
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SYSCTL_CLKOUTSRC_MAINSYSCLK, /*!< Main (B) system clock for CLKOUT */
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SYSCTL_CLKOUTSRC_USBPLLOUT = 5, /*!< USB PLL out */
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SYSCTL_CLKOUTSRC_SCTPLLOUT, /*!< SCT PLL out */
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SYSCTL_CLKOUTSRC_RTC32K /*!< RTC 32 kHz output */
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} CHIP_SYSCTL_CLKOUTSRC_T;
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/**
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* @brief Set CLKOUT clock source and divider
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* @param src : Clock source for CLKOUT
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* @param div : divider for CLKOUT clock
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* @return Nothing
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* @note Use 0 to disable, or a divider value of 1 to 255. The CLKOUT clock
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* rate is the clock source divided by the divider. This function will
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* also toggle the clock source update register to update the clock
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* source.
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*/
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void Chip_Clock_SetCLKOUTSource(CHIP_SYSCTL_CLKOUTSRC_T src, uint32_t div);
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/**
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* @}
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*/
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/** @defgroup CLOCK_15XX_CHIP_PLL: PLL setup functions
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* @{
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*/
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/**
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* Clock sources for system, USB, and SCT PLLs
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*/
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typedef enum CHIP_SYSCTL_PLLCLKSRC {
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SYSCTL_PLLCLKSRC_IRC = 0, /*!< Internal oscillator in (may not work for USB) */
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SYSCTL_PLLCLKSRC_MAINOSC, /*!< Crystal (main) oscillator in */
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SYSCTL_PLLCLKSRC_SYSOSC = SYSCTL_PLLCLKSRC_MAINOSC,
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SYSCTL_PLLCLKSRC_RESERVED1, /*!< Reserved */
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SYSCTL_PLLCLKSRC_RESERVED2, /*!< Reserved */
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} CHIP_SYSCTL_PLLCLKSRC_T;
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/**
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* @brief Set System PLL clock source
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* @param src : Clock source for system PLL
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* @return Nothing
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*/
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STATIC INLINE void Chip_Clock_SetSystemPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src)
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{
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LPC_SYSCTL->SYSPLLCLKSEL = (uint32_t) src;
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}
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/**
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* @brief Set System PLL divider values
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* @param msel : PLL feedback divider value. M = msel + 1.
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* @param psel : PLL post divider value. P = (1<<psel).
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* @return Nothing
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* @note See the user manual for how to setup the PLL.
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*/
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STATIC INLINE void Chip_Clock_SetupSystemPLL(uint8_t msel, uint8_t psel)
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{
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LPC_SYSCTL->SYSPLLCTRL = (msel & 0x3F) | ((psel & 0x3) << 6);
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}
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/**
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* @brief Read System PLL lock status
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* @return true of the PLL is locked. false if not locked
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*/
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STATIC INLINE bool Chip_Clock_IsSystemPLLLocked(void)
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{
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return (bool) ((LPC_SYSCTL->SYSPLLSTAT & 1) != 0);
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}
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/**
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* @brief Return System PLL input clock rate
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* @return System PLL input clock rate
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*/
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uint32_t Chip_Clock_GetSystemPLLInClockRate(void);
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/**
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* @brief Return System PLL output clock rate
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* @return System PLL output clock rate
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*/
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uint32_t Chip_Clock_GetSystemPLLOutClockRate(void);
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/**
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* @brief Set USB PLL clock source
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* @param src : Clock source for USB PLL
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* @return Nothing
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*/
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STATIC INLINE void Chip_Clock_SetUSBPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src)
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{
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LPC_SYSCTL->USBPLLCLKSEL = (uint32_t) src;
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}
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/**
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* @brief Set USB PLL divider values
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* @param msel : PLL feedback divider value. M = msel + 1.
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* @param psel : PLL post divider value. P = (1<<psel).
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* @return Nothing
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* @note See the user manual for how to setup the PLL.
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*/
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STATIC INLINE void Chip_Clock_SetupUSBPLL(uint8_t msel, uint8_t psel)
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{
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LPC_SYSCTL->USBPLLCTRL = (msel & 0x3F) | ((psel & 0x3) << 6);
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}
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/**
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* @brief Read USB PLL lock status
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* @return true of the PLL is locked. false if not locked
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*/
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STATIC INLINE bool Chip_Clock_IsUSBPLLLocked(void)
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{
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return (bool) ((LPC_SYSCTL->USBPLLSTAT & 1) != 0);
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}
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/**
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* @brief Return USB PLL input clock rate
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* @return USB PLL input clock rate
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*/
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uint32_t Chip_Clock_GetUSBPLLInClockRate(void);
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/**
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* @brief Return USB PLL output clock rate
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* @return USB PLL output clock rate
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*/
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uint32_t Chip_Clock_GetUSBPLLOutClockRate(void);
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/**
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* @brief Set SCT PLL clock source
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* @param src : Clock source for SCT PLL
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* @return Nothing
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*/
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STATIC INLINE void Chip_Clock_SetSCTPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src)
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{
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LPC_SYSCTL->SCTPLLCLKSEL = (uint32_t) src;
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}
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/**
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* @brief Set SCT PLL divider values
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* @param msel : PLL feedback divider value. M = msel + 1.
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* @param psel : PLL post divider value. P = (1<<psel).
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* @return Nothing
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* @note See the user manual for how to setup the PLL.
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*/
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STATIC INLINE void Chip_Clock_SetupSCTPLL(uint8_t msel, uint8_t psel)
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{
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LPC_SYSCTL->SCTPLLCTRL = (msel & 0x3F) | ((psel & 0x3) << 6);
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}
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/**
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* @brief Read SCT PLL lock status
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* @return true of the PLL is locked. false if not locked
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*/
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STATIC INLINE bool Chip_Clock_IsSCTPLLLocked(void)
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{
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return (bool) ((LPC_SYSCTL->SCTPLLSTAT & 1) != 0);
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}
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/**
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* @brief Return SCT PLL input clock rate
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* @return SCT PLL input clock rate
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*/
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uint32_t Chip_Clock_GetSCTPLLInClockRate(void);
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/**
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* @brief Return SCT PLL output clock rate
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* @return SCT PLL output clock rate
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*/
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uint32_t Chip_Clock_GetSCTPLLOutClockRate(void);
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/**
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* @}
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*/
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/** @defgroup CLOCK_15XX_CHIP_SUP: Clock support functions
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* Functions in this group include oscillator control and rates, peripheral
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* clock control, and peripheral dividers.
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* @{
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*/
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/**
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* @brief Set system clock divider
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* @param div : divider for system clock
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* @return Nothing
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* @note Use 0 to disable, or a divider value of 1 to 255. The system clock
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* rate is the main system clock divided by this value.
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*/
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STATIC INLINE void Chip_Clock_SetSysClockDiv(uint32_t div)
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{
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LPC_SYSCTL->SYSAHBCLKDIV = div;
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}
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/**
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* System and peripheral clocks
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*/
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typedef enum CHIP_SYSCTL_CLOCK {
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/* Peripheral clock enables for SYSAHBCLKCTRL0 */
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SYSCTL_CLOCK_SYS = 0, /*!< System clock */
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SYSCTL_CLOCK_ROM, /*!< ROM clock */
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SYSCTL_CLOCK_SRAM1 = 3, /*!< SRAM1 clock */
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SYSCTL_CLOCK_SRAM2, /*!< SRAM2 clock */
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SYSCTL_CLOCK_FLASH = 7, /*!< FLASH controller clock */
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SYSCTL_CLOCK_EEPROM = 9, /*!< EEPROM controller clock */
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SYSCTL_CLOCK_MUX = 11, /*!< Input mux clock */
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SYSCTL_CLOCK_SWM, /*!< Switch matrix clock */
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SYSCTL_CLOCK_IOCON, /*!< IOCON clock */
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SYSCTL_CLOCK_GPIO0, /*!< GPIO0 clock */
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SYSCTL_CLOCK_GPIO1, /*!< GPIO1 clock */
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SYSCTL_CLOCK_GPIO2, /*!< GPIO2 clock */
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SYSCTL_CLOCK_PININT = 18, /*!< PININT clock */
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SYSCTL_CLOCK_GINT, /*!< grouped pin interrupt block clock */
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SYSCTL_CLOCK_DMA, /*!< DMA clock */
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SYSCTL_CLOCK_CRC, /*!< CRC clock */
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SYSCTL_CLOCK_WDT, /*!< WDT clock */
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SYSCTL_CLOCK_RTC, /*!< RTC clock */
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SYSCTL_CLOCK_ADC0 = 27, /*!< ADC0 clock */
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SYSCTL_CLOCK_ADC1, /*!< ADC1 clock */
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SYSCTL_CLOCK_DAC, /*!< DAC clock */
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SYSCTL_CLOCK_ACMP, /*!< ACMP clock */
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/* Peripheral clock enables for SYSAHBCLKCTRL1 */
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SYSCTL_CLOCK_MRT = 32, /*!< multi-rate timer clock */
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SYSCTL_CLOCK_RIT, /*!< repetitive interrupt timer clock */
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SYSCTL_CLOCK_SCT0, /*!< SCT0 clock */
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SYSCTL_CLOCK_SCT1, /*!< SCT1 clock */
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SYSCTL_CLOCK_SCT2, /*!< SCT2 clock */
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SYSCTL_CLOCK_SCT3, /*!< SCT3 clock */
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SYSCTL_CLOCK_SCTIPU, /*!< SCTIPU clock */
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SYSCTL_CLOCK_CAN, /*!< CAN clock */
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SYSCTL_CLOCK_SPI0 = 32 + 9, /*!< SPI0 clock */
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SYSCTL_CLOCK_SPI1, /*!< SPI1 clock */
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SYSCTL_CLOCK_I2C0 = 32 + 13, /*!< I2C0 clock */
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SYSCTL_CLOCK_UART0 = 32 + 17, /*!< UART0 clock */
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SYSCTL_CLOCK_UART1, /*!< UART1 clock */
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SYSCTL_CLOCK_UART2, /*!< UART2 clock */
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SYSCTL_CLOCK_QEI = 32 + 21, /*!< QEI clock */
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SYSCTL_CLOCK_USB = 32 + 23, /*!< USB clock */
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} CHIP_SYSCTL_CLOCK_T;
|
|
|
|
/**
|
|
* @brief Enable a system or peripheral clock
|
|
* @param clk : Clock to enable
|
|
* @return Nothing
|
|
*/
|
|
void Chip_Clock_EnablePeriphClock(CHIP_SYSCTL_CLOCK_T clk);
|
|
|
|
/**
|
|
* @brief Disable a system or peripheral clock
|
|
* @param clk : Clock to disable
|
|
* @return Nothing
|
|
*/
|
|
void Chip_Clock_DisablePeriphClock(CHIP_SYSCTL_CLOCK_T clk);
|
|
|
|
/**
|
|
* @brief Set system tick clock divider
|
|
* @param div : divider for system clock
|
|
* @return Nothing
|
|
* @note Use 0 to disable, or a divider value of 1 to 255. The system tick
|
|
* rate is the main system clock divided by this value. Use caution when using
|
|
* the CMSIS SysTick_Config() functions as they typically use SystemCoreClock
|
|
* for setup.
|
|
*/
|
|
STATIC INLINE void Chip_Clock_SetSysTickClockDiv(uint32_t div)
|
|
{
|
|
LPC_SYSCTL->SYSTICKCLKDIV = div;
|
|
}
|
|
|
|
/**
|
|
* @brief Returns system tick clock divider
|
|
* @return system tick clock divider
|
|
*/
|
|
STATIC INLINE uint32_t Chip_Clock_GetSysTickClockDiv(void)
|
|
{
|
|
return LPC_SYSCTL->SYSTICKCLKDIV;
|
|
}
|
|
|
|
/**
|
|
* @brief Returns the system tick rate as used with the system tick divider
|
|
* @return the system tick rate
|
|
*/
|
|
uint32_t Chip_Clock_GetSysTickClockRate(void);
|
|
|
|
/**
|
|
* @brief Set IOCON glitch filter clock divider value
|
|
* @param div : value for IOCON filter divider
|
|
* @return Nothing
|
|
* @note Use 0 to disable, or a divider value of 1 to 255.
|
|
*/
|
|
STATIC INLINE void Chip_Clock_SetIOCONFiltClockDiv(uint32_t div)
|
|
{
|
|
LPC_SYSCTL->IOCONCLKDIV = div;
|
|
}
|
|
|
|
/**
|
|
* @brief Return IOCON glitch filter clock divider value
|
|
* @return IOCON glitch filter clock divider value
|
|
*/
|
|
STATIC INLINE uint32_t Chip_Clock_GetIOCONFiltClockDiv(void)
|
|
{
|
|
return LPC_SYSCTL->IOCONCLKDIV;
|
|
}
|
|
|
|
/**
|
|
* @brief Set Asynchronous ADC clock divider value
|
|
* @param div : value for UART fractional generator multiplier value
|
|
* @return Nothing
|
|
* @note Use 0 to disable, or a divider value of 1 to 255.
|
|
*/
|
|
STATIC INLINE void Chip_Clock_SetADCASYNCClockDiv(uint32_t div)
|
|
{
|
|
LPC_SYSCTL->ADCASYNCCLKDIV = div;
|
|
}
|
|
|
|
/**
|
|
* @brief Return Asynchronous ADC clock divider value
|
|
* @return Asynchronous ADC clock divider value
|
|
*/
|
|
STATIC INLINE uint32_t Chip_Clock_GetADCASYNCClockDiv(void)
|
|
{
|
|
return LPC_SYSCTL->ADCASYNCCLKDIV;
|
|
}
|
|
|
|
/**
|
|
* @brief Set UART base rate base rate (up to main clock rate) (all UARTs)
|
|
* @param rate : Desired rate for fractional divider/multipler output
|
|
* @param fEnable : true to use fractional clocking, false for integer clocking
|
|
* @return Actual rate generated
|
|
* @note All UARTs use the same base clock for their baud rate
|
|
* basis. This function is used to generate that clock, while the
|
|
* UART driver's SetBaud functions will attempt to get the closest
|
|
* baud rate from this base clock without altering it. This needs
|
|
* to be setup prior to individual UART setup.<br>
|
|
* UARTs need a base clock 16x faster than the baud rate, so if you
|
|
* need a 115.2Kbps baud rate, you will need a clock rate of at
|
|
* least (115.2K * 16). The UART base clock is generated from the
|
|
* main system clock, so fractional clocking may be the only
|
|
* possible choice when using a low main system clock frequency.
|
|
* Do not alter the FRGCTRL or UARTCLKDIV registers after this call.
|
|
*/
|
|
uint32_t Chip_Clock_SetUARTBaseClockRate(uint32_t rate, bool fEnable);
|
|
|
|
/**
|
|
* @brief Get UART base rate (all UARTs)
|
|
* @return UART base rate in Hz
|
|
*/
|
|
uint32_t Chip_Clock_GetUARTBaseClockRate(void);
|
|
|
|
/**
|
|
* @brief Set The UART Fractional Generator Divider (all UARTs)
|
|
* @param div : Fractional Generator Divider value, should be 0xFF
|
|
* @return Nothing
|
|
*/
|
|
STATIC INLINE void Chip_Clock_SetUARTFRGDivider(uint8_t div)
|
|
{
|
|
LPC_SYSCTL->UARTCLKDIV = (uint32_t) div;
|
|
}
|
|
|
|
/**
|
|
* @brief Get The UART Fractional Generator Divider (all UARTs)
|
|
* @return Value of UART Fractional Generator Divider
|
|
*/
|
|
STATIC INLINE uint32_t Chip_Clock_GetUARTFRGDivider(void)
|
|
{
|
|
return LPC_SYSCTL->UARTCLKDIV;
|
|
}
|
|
|
|
/**
|
|
* @brief Enable the RTC 32KHz output
|
|
* @return Nothing
|
|
* @note This clock can be used for the main clock directly, but
|
|
* do not use this clock with the system PLL.
|
|
*/
|
|
STATIC INLINE void Chip_Clock_EnableRTCOsc(void)
|
|
{
|
|
LPC_SYSCTL->RTCOSCCTRL = 1;
|
|
}
|
|
|
|
/**
|
|
* @brief Disable the RTC 32KHz output
|
|
* @return Nothing
|
|
*/
|
|
STATIC INLINE void Chip_Clock_DisableRTCOsc(void)
|
|
{
|
|
LPC_SYSCTL->RTCOSCCTRL = 0;
|
|
}
|
|
|
|
/**
|
|
* @brief Returns the main oscillator clock rate
|
|
* @return main oscillator clock rate in Hz
|
|
*/
|
|
STATIC INLINE uint32_t Chip_Clock_GetMainOscRate(void)
|
|
{
|
|
return OscRateIn;
|
|
}
|
|
|
|
/**
|
|
* @brief Returns the internal oscillator (IRC) clock rate
|
|
* @return internal oscillator (IRC) clock rate in Hz
|
|
*/
|
|
STATIC INLINE uint32_t Chip_Clock_GetIntOscRate(void)
|
|
{
|
|
return SYSCTL_IRC_FREQ;
|
|
}
|
|
|
|
/**
|
|
* @brief Returns the RTC clock rate
|
|
* @return RTC oscillator clock rate in Hz
|
|
*/
|
|
STATIC INLINE uint32_t Chip_Clock_GetRTCOscRate(void)
|
|
{
|
|
return RTCOscRateIn;
|
|
}
|
|
|
|
/**
|
|
* @brief Return estimated watchdog oscillator rate
|
|
* @return Estimated watchdog oscillator rate
|
|
* @note This rate is accurate to plus or minus 40%.
|
|
*/
|
|
STATIC INLINE uint32_t Chip_Clock_GetWDTOSCRate(void)
|
|
{
|
|
return SYSCTL_WDTOSC_FREQ;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup CLOCK_15XX_CHIP_MISC: Misc clock functions
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Bypass System Oscillator and set oscillator frequency range
|
|
* @param bypass : Flag to bypass oscillator
|
|
* @param highfr : Flag to set oscillator range from 15-25 MHz
|
|
* @return Nothing
|
|
* @note Sets the PLL input to bypass the oscillator. This would be
|
|
* used if an external clock that is not an oscillator is attached
|
|
* to the XTALIN pin.
|
|
*/
|
|
void Chip_Clock_SetPLLBypass(bool bypass, bool highfr);
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* __CLOCK_15XX_H_ */
|