207 lines
9.6 KiB
C
207 lines
9.6 KiB
C
/*
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* @brief LPC15xx DMA ROM API declarations and functions
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2013
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __ROM_DMA_15XX_H_
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#define __ROM_DMA_15XX_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup DMAROM_15XX CHIP: LPC15xx DMA ROM API declarations and functions
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* @ingroup ROMAPI_15XX
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* @{
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*/
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/* Bit definitions for DMA ROM Channel Configuration Structure */
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#define DMA_ROM_CH_EVENT_SWTRIG ((uint8_t) 0)
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#define DMA_ROM_CH_EVENT_PERIPH ((uint8_t) 1)
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#define DMA_ROM_CH_EVENT_HWTRIG ((uint8_t) 2)
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#define DMA_ROM_CH_HWTRIG_BURSTPOWER_1 ((uint8_t) 0 << 0)
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#define DMA_ROM_CH_HWTRIG_BURSTPOWER_2 ((uint8_t) 1 << 0)
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#define DMA_ROM_CH_HWTRIG_BURSTPOWER_4 ((uint8_t) 2 << 0)
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#define DMA_ROM_CH_HWTRIG_BURSTPOWER_8 ((uint8_t) 3 << 0)
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#define DMA_ROM_CH_HWTRIG_BURSTPOWER_16 ((uint8_t) 4 << 0)
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#define DMA_ROM_CH_HWTRIG_BURSTPOWER_32 ((uint8_t) 5 << 0)
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#define DMA_ROM_CH_HWTRIG_BURSTPOWER_64 ((uint8_t) 6 << 0)
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#define DMA_ROM_CH_HWTRIG_BURSTPOWER_128 ((uint8_t) 7 << 0)
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#define DMA_ROM_CH_HWTRIG_BURSTPOWER_256 ((uint8_t) 8 << 0)
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#define DMA_ROM_CH_HWTRIG_BURSTPOWER_512 ((uint8_t) 9 << 0)
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#define DMA_ROM_CH_HWTRIG_BURSTPOWER_1024 ((uint8_t) 10 << 0)
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#define DMA_ROM_CH_HWTRIG_SRC_WRAP_EN ((uint8_t) 1 << 4)
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#define DMA_ROM_CH_HWTRIG_DEST_WRAP_EN ((uint8_t) 1 << 5)
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#define DMA_ROM_CH_HWTRIG_BURST_EN ((uint8_t) 1 << 6)
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/* Bit definitions for DMA ROM Task Configuration Structure */
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#define DMA_ROM_TASK_CFG_PING_PONG_EN ((uint8_t) 1 << 0)
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#define DMA_ROM_TASK_CFG_SW_TRIGGER ((uint8_t) 1 << 1)
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#define DMA_ROM_TASK_CFG_CLR_TRIGGER ((uint8_t) 1 << 2)
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#define DMA_ROM_TASK_CFG_SEL_INTA ((uint8_t) 1 << 3)
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#define DMA_ROM_TASK_CFG_SEL_INTB ((uint8_t) 1 << 4)
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#define DMA_ROM_TASK_DATA_WIDTH_8 ((uint8_t) 0 )
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#define DMA_ROM_TASK_DATA_WIDTH_16 ((uint8_t) 1 )
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#define DMA_ROM_TASK_DATA_WIDTH_32 ((uint8_t) 2 )
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#define DMA_ROM_TASK_SRC_INC_0 ((uint8_t) 0 << 2)
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#define DMA_ROM_TASK_SRC_INC_1 ((uint8_t) 1 << 2)
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#define DMA_ROM_TASK_SRC_INC_2 ((uint8_t) 2 << 2)
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#define DMA_ROM_TASK_SRC_INC_4 ((uint8_t) 3 << 2)
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#define DMA_ROM_TASK_DEST_INC_0 ((uint8_t) 0 << 4)
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#define DMA_ROM_TASK_DEST_INC_1 ((uint8_t) 1 << 4)
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#define DMA_ROM_TASK_DEST_INC_2 ((uint8_t) 2 << 4)
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#define DMA_ROM_TASK_DEST_INC_4 ((uint8_t) 3 << 4)
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/**
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* @brief DMA handle type
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*/
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typedef void *DMA_HANDLE_T;
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/**
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* @brief DMA channel callback function type
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* @param res0: error code
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* @param res1: 0 = INTA is issued, 1 = INTB is issued
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*/
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typedef void (*CALLBK_T)(uint32_t res0, uint32_t res1);
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/**
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* @brief DMA ROM drivers channel control structure
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*/
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typedef struct {
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uint8_t event; /*!< event type selection for DMA transfer
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- 0: software request
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- 1: peripheral request
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- 2: hardware trigger
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- others: reserved */
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uint8_t hd_trigger; /*!< In case hardware trigger is enabled, the trigger burst is setup here.
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NOTE: Rising edge triggered is fixed
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- bit0~bit3: burst size
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- 0: burst size =1, 1: 2^1, 2: 2^2,... 10: 1024, others: reserved.
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- bit4: Source Burst Wrap
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- 0: Source burst wrapping is not enabled
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- 1: Source burst wrapping is enabled
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- bit5: Destination Burst Wrap
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- 0: Destination burst wrapping is not enabled
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- 1: Destination burst wrapping is enabled
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- bit6: Trigger Burst
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- 0: Hardware trigger cause a single transfer
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- 1: Hardware trigger cause a burst transfer
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- bit7: reserved */
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uint8_t priority; /*!< priority level
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- 0 -> 7: Highest priority -> Lowest priority.
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- other: reserved. */
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uint8_t reserved0;
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CALLBK_T cb_func; /*!< callback function, Callback function is
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only invoked when INTA or INTB is enabled. */
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} DMA_CHANNEL_T;
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/**
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* @brief DMA ROM driver's TASK parameter structure
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*/
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typedef struct {
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uint8_t ch_num; /*!< DMA channel number */
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uint8_t config; /*!< configuration of this task
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- bit0: Ping_Pong transfer
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- 0: Not Ping_Pong transfer
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- 1: Linked with previous task for Ping_Pong transfer
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- bit1: Software Trigger.
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- 0: the trigger for this channel is not set.
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- 1: the trigger for this channel is set immediately.
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- bit2: Clear Trigger
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- 0: The trigger is not cleared when this task is finished.
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- 1: The trigger is cleared when this task is finished.
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- bit3: Select INTA
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- 0: No IntA.
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- 1: The IntB flag for this channel will be set when this task is finished.
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bit4: Select INTB
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0: No IntB.
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1: The IntB flag for this channel will be set when this task is finished.
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bit5~bit7: reserved
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*/
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uint8_t data_type; /*!<
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- bit0~bit1: Data width. 0: 8-bit, 1: 16-bit, 2: 32-bit, 3: reserved
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- bit2~bit3: How is source address incremented?
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- 0: The source address is not incremented for each transfer.
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1: The source address is incremented by the amount specified by Width for each transfer.
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2: The source address is incremented by 2 times the amount specified by Width for each transfer.
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3: The source address is incremented by 4 times the amount specified by Width for each transfer.
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- bit4~bit5: How is the destination address incremented?
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0: The destination address is not incremented for each transfer.
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1: The destination address is incremented by the amount specified by Width for each transfer.
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2: The destination address is incremented by 2 times the amount specified by Width for each transfer.
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3: The destination address is incremented by 4 times the amount specified by Width for each transfer.
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- bit6~bit7: reserved. */
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uint8_t reserved0;
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uint16_t data_length; /*!< 0: 1 transfer, 1: 2 transfer, ..., 1023: 1024 transfer. Others: reserved.*/
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uint16_t reserved1;
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uint32_t src; /*!< Source data end address */
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uint32_t dst; /*!< Destination end address */
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uint32_t task_addr; /*!< the address of RAM for saving this task.
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(NOTE: each task need 16 bytes RAM for storing configuration,
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and DMA API could set it according user input parameter,
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but it is responsible of user to allocate this RAM space and
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make sure that the base address must be 16-byte alignment.
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And if user has setup the next_task(!=0), the dma_task_link
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must be called for this task setup, otherwise unpredictable error will happen.) */
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} DMA_TASK_T;
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/**
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* @brief DMA ROM API structure
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* The DMA API handles DMA set-up and transfers.
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*/
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typedef struct DMAD_API {
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/** DMA ISR routine */
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void (*dma_isr)(DMA_HANDLE_T *handle);
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/** Get memory size needed for DMA. */
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uint32_t (*dma_get_mem_size)(void);
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/** Set up DMA. */
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DMA_HANDLE_T * (*dma_setup)(uint32_t base_addr, uint8_t * ram);
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/** Enable DMA channel and set-up basic DMA transfer. */
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ErrorCode_t (*dma_init)(DMA_HANDLE_T *handle, DMA_CHANNEL_T *channel, DMA_TASK_T *task);
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/** Create linked transfer. */
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ErrorCode_t (*dma_link)(DMA_HANDLE_T *handle, DMA_TASK_T *task, uint8_t valid);
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/** Set a task to valid. */
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ErrorCode_t (*dma_set_valid)(DMA_HANDLE_T *handle, uint8_t chl_num);
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/** Pause DMA transfer on a given channel. */
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ErrorCode_t (*dma_pause)(DMA_HANDLE_T *handle, uint8_t chl_num);
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/** Resume DMA transfer. */
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ErrorCode_t (*dma_unpause)(DMA_HANDLE_T *handle, uint8_t chl_num);
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/** Cancel DMA transfer on a given channel.*/
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ErrorCode_t (*dma_abort)(DMA_HANDLE_T *handle, uint8_t chl_num);
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} DMAD_API_T;
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ROM_DMA_15XX_H_ */
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