316 lines
10 KiB
C
316 lines
10 KiB
C
/*
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* @brief LPC15xx Input Mux Registers and Driver
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2013
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __INMUX_15XX_H_
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#define __INMUX_15XX_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup INMUX_15XX CHIP: LPC15xx Input Mux Registers and Driver
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* @ingroup CHIP_15XX_Drivers
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* @{
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*/
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/**
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* @brief LPC15xx Input Mux Register Block Structure
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*/
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typedef struct { /*!< INMUX Structure */
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__IO uint32_t SCT0_INMUX[7]; /*!< Input mux registers for SCT0 inputs */
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__I uint32_t RESERVED1[1];
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__IO uint32_t SCT1_INMUX[7]; /*!< Input mux registers for SCT1 inputs */
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__I uint32_t RESERVED2[1];
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__IO uint32_t SCT2_INMUX[3]; /*!< Input mux registers for SCT2 inputs */
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__I uint32_t RESERVED3[5];
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__IO uint32_t SCT3_INMUX[3]; /*!< Input mux registers for SCT3 inputs */
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__I uint32_t RESERVED4[5];
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__I uint32_t RESERVED4A[16];
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__IO uint32_t PINTSEL[8]; /*!< Pin interrupt select registers */
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__IO uint32_t DMA_ITRIG_INMUX[18]; /*!< Input mux register for DMA trigger inputs */
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__I uint32_t RESERVED5[6];
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__IO uint32_t DMA_INMUX[4]; /*!< Input mux register for DMA trigger inputs */
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__I uint32_t RESERVED6[4];
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__IO uint32_t FREQMEAS_REF; /*!< Clock selection for frequency measurement ref clock */
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__IO uint32_t FREQMEAS_TARGET; /*!< Clock selection for frequency measurement target clock */
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} LPC_INMUX_T;
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/* SCT input mux mapping selections for SCT0 inputs 0-6 */
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typedef enum {
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SCT0_INMUX_PIO0_2 = 0,
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SCT0_INMUX_PIO0_3,
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SCT0_INMUX_PIO0_17,
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SCT0_INMUX_PIO0_30,
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SCT0_INMUX_PIO1_6,
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SCT0_INMUX_PIO1_7,
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SCT0_INMUX_PIO1_12,
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SCT0_INMUX_PIO1_13,
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SCT0_INMUX_SCT1_OUT4,
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SCT0_INMUX_SCT2_OUT4,
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SCT0_INMUX_SCT2_OUT5,
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SCT0_INMUX_ADC0_THCMP_IRQ,
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SCT0_INMUX_ADC1_THCMP_IRQ,
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SCT0_INMUX_ACMP0_OUT,
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SCT0_INMUX_ACMP1_OUT,
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SCT0_INMUX_ACMP2_OUT,
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SCT0_INMUX_ACMP3_OUT,
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SCT0_INMUX_SCTIPU_ABORT,
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SCT0_INMUX_SCTIPU_SAMPLE0,
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SCT0_INMUX_SCTIPU_SAMPLE1,
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SCT0_INMUX_SCTIPU_SAMPLE2,
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SCT0_INMUX_SCTIPU_SAMPLE3,
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SCT0_INMUX_DEBUG_HALTED
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} SCT0_INMUX_T;
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/**
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* @brief Selects an input source for SCT0 input 0 to 6
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* @param input : SCT0 input to use, 0 - 6
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* @param src : Source to map to the SCT input
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* @return Nothing
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*/
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STATIC INLINE void Chip_INMUX_SelectSCT0Src(uint8_t input, SCT0_INMUX_T src)
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{
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LPC_INMUX->SCT0_INMUX[input] = (uint32_t) src;
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}
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/* SCT input mux mapping selections for SCT1 inputs 0-6 */
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typedef enum {
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SCT1_INMUX_PIO0_15 = 0,
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SCT1_INMUX_PIO0_16,
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SCT1_INMUX_PIO0_21,
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SCT1_INMUX_PIO0_31,
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SCT1_INMUX_PIO1_4,
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SCT1_INMUX_PIO1_5,
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SCT1_INMUX_PIO1_15,
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SCT1_INMUX_PIO1_16,
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SCT1_INMUX_SCT0_OUT4,
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SCT1_INMUX_SCT3_OUT4,
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SCT1_INMUX_SCT3_OUT5,
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SCT1_INMUX_ADC0_THCMP_IRQ,
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SCT1_INMUX_ADC1_THCMP_IRQ,
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SCT1_INMUX_ACMP0_OUT,
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SCT1_INMUX_ACMP1_OUT,
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SCT1_INMUX_ACMP2_OUT,
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SCT1_INMUX_ACMP3_OUT,
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SCT1_INMUX_SCTIPU_ABORT,
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SCT1_INMUX_SCTIPU_SAMPLE0,
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SCT1_INMUX_SCTIPU_SAMPLE1,
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SCT1_INMUX_SCTIPU_SAMPLE2,
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SCT1_INMUX_SCTIPU_SAMPLE3,
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SCT1_INMUX_DEBUG_HALTED
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} SCT1_INMUX_T;
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/**
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* @brief Selects an input source for SCT1 input 0 to 6
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* @param input : SCT1 input to use, 0 - 6
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* @param src : Source to map to the SCT input
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* @return Nothing
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*/
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STATIC INLINE void Chip_INMUX_SelectSCT1Src(uint8_t input, SCT1_INMUX_T src)
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{
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LPC_INMUX->SCT1_INMUX[input] = (uint32_t) src;
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}
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/* SCT input mux mapping selections for SCT2 inputs 0-2 */
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typedef enum {
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SCT2_INMUX_PIO0_4 = 0,
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SCT2_INMUX_PIO0_27,
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SCT2_INMUX_PIO1_18,
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SCT2_INMUX_PIO1_19,
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SCT2_INMUX_SCT0_OUT4,
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SCT2_INMUX_SCT0_OUT5,
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SCT2_INMUX_SCT0_OUT7,
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SCT2_INMUX_SCT0_OUT8,
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SCT2_INMUX_ADC0_THCMP_IRQ,
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SCT2_INMUX_ADC1_THCMP_IRQ,
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SCT2_INMUX_ACMP0_OUT,
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SCT2_INMUX_ACMP1_OUT,
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SCT2_INMUX_ACMP2_OUT,
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SCT2_INMUX_ACMP3_OUT,
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SCT2_INMUX_SCTIPU_ABORT,
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SCT2_INMUX_SCTIPU_SAMPLE0,
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SCT2_INMUX_SCTIPU_SAMPLE1,
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SCT2_INMUX_SCTIPU_SAMPLE2,
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SCT2_INMUX_SCTIPU_SAMPLE3,
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SCT2_INMUX_USB_FRAME_TOGGLE,
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SCT2_INMUX_DEBUG_HALTED
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} SCT2_INMUX_T;
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/**
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* @brief Selects an input source for SCT2 input 0 to 2
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* @param input : SCT2 input to use, 0 - 2
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* @param src : Source to map to the SCT input
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* @return Nothing
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*/
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STATIC INLINE void Chip_INMUX_SelectSCT2Src(uint8_t input, SCT2_INMUX_T src)
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{
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LPC_INMUX->SCT2_INMUX[input] = (uint32_t) src;
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}
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/* SCT input mux mapping selections for SCT3 inputs 0-2 */
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typedef enum {
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SCT3_INMUX_PIO0_7 = 0,
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SCT3_INMUX_PIO1_11,
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SCT3_INMUX_PIO1_21,
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SCT3_INMUX_PIO1_22,
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SCT3_INMUX_SCT1_OUT4,
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SCT3_INMUX_SCT1_OUT5,
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SCT3_INMUX_SCT1_OUT7,
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SCT3_INMUX_SCT1_OUT8,
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SCT3_INMUX_ADC0_THCMP_IRQ,
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SCT3_INMUX_ADC1_THCMP_IRQ,
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SCT3_INMUX_ACMP0_OUT,
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SCT3_INMUX_ACMP1_OUT,
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SCT3_INMUX_ACMP2_OUT,
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SCT3_INMUX_ACMP3_OUT,
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SCT3_INMUX_SCTIPU_ABORT3,
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SCT3_INMUX_SCTIPU_SAMPLE0,
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SCT3_INMUX_SCTIPU_SAMPLE1,
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SCT3_INMUX_SCTIPU_SAMPLE2,
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SCT3_INMUX_SCTIPU_SAMPLE3,
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SCT3_INMUX_USB_FRAME_TOGGLE,
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SCT3_INMUX_DEBUG_HALTED
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} SCT3_INMUX_T;
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/**
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* @brief Selects an input source for SCT3 input 0 to 2
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* @param input : SCT3 input to use, 0 - 2
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* @param src : Source to map to the SCT input
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* @return Nothing
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*/
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STATIC INLINE void Chip_INMUX_SelectSCT3Src(uint8_t input, SCT3_INMUX_T src)
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{
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LPC_INMUX->SCT3_INMUX[input] = (uint32_t) src;
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}
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/**
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* @brief GPIO Pin Interrupt Pin Select (sets PINTSEL register)
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* @param pintSel : GPIO PINTSEL interrupt, should be: 0 to 7
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* @param portNum : GPIO port number interrupt, should be: 0 to 1
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* @param pinNum : GPIO pin number Interrupt, should be: 0 to 31
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* @return Nothing
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*/
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STATIC INLINE void Chip_INMUX_PinIntSel(uint8_t pintSel, uint8_t portNum, uint8_t pinNum)
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{
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LPC_INMUX->PINTSEL[pintSel] = (portNum * 32) + pinNum;
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}
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/* DMA triggers that can mapped to DMA channels */
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typedef enum {
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DMATRIG_ADC0_SEQA_IRQ = 0, /*!< ADC0 sequencer A interrupt as trigger */
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DMATRIG_ADC0_SEQB_IRQ, /*!< ADC0 sequencer B interrupt as trigger */
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DMATRIG_ADC1_SEQA_IRQ, /*!< ADC1 sequencer A interrupt as trigger */
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DMATRIG_ADC1_SEQB_IRQ, /*!< ADC1 sequencer B interrupt as trigger */
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DMATRIG_SCT0_DMA0, /*!< SCT 0, DMA 0 as trigger */
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DMATRIG_SCT0_DMA1, /*!< SCT 1, DMA 1 as trigger */
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DMATRIG_SCT1_DMA0, /*!< SCT 0, DMA 0 as trigger */
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DMATRIG_SCT1_DMA1, /*!< SCT 1, DMA 1 as trigger */
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DMATRIG_SCT2_DMA0, /*!< SCT 2, DMA 0 as trigger */
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DMATRIG_SCT2_DMA1, /*!< SCT 2, DMA 1 as trigger */
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DMATRIG_SCT3_DMA0, /*!< SCT 3, DMA 0 as trigger */
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DMATRIG_SCT3_DMA1, /*!< SCT 3, DMA 1 as trigger */
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DMATRIG_ACMP0_OUT, /*!< Analog comparator 0 output as trigger */
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DMATRIG_ACMP1_OUT, /*!< Analog comparator 1 output as trigger */
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DMATRIG_ACMP2_OUT, /*!< Analog comparator 2 output as trigger */
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DMATRIG_ACMP3_OUT, /*!< Analog comparator 3 output as trigger */
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DMATRIG_OUTMUX0, /*!< DMA trigger tied to this source, Select with Chip_INMUX_SetDMAOutMux */
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DMATRIG_OUTMUX1, /*!< DMA trigger tied to this source, Select with Chip_INMUX_SetDMAOutMux */
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DMATRIG_OUTMUX2, /*!< DMA trigger tied to this source, Select with Chip_INMUX_SetDMAOutMux */
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DMATRIG_OUTMUX3 /*!< DMA trigger tied to this source, Select with Chip_INMUX_SetDMAOutMux */
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} DMA_TRIGSRC_T;
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/**
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* @brief Select a trigger source for a DMA channel
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* @param ch : DMA channel number
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* @param trig : Trigger source for the DMA channel
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* @return Nothing
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*/
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STATIC INLINE void Chip_INMUX_SetDMATrigger(uint8_t ch, DMA_TRIGSRC_T trig)
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{
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LPC_INMUX->DMA_ITRIG_INMUX[ch] = (uint32_t) trig;
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}
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/**
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* @brief Selects a DMA trigger source for the DMATRIG_OUTMUXn IDs
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* @param index : Select 0 to 3 to sets the source for DMATRIG_OUTMUX0 to DMATRIG_OUTMUX3
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* @param dmaCh : DMA channel to select for DMATRIG_OUTMUXn source
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* @return Nothing
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* @note This function sets the DMA trigger (out) source used with the DMATRIG_OUTMUXn
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* trigger source.
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*/
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STATIC INLINE void Chip_INMUX_SetDMAOutMux(uint8_t index, uint8_t dmaCh)
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{
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LPC_INMUX->DMA_INMUX[index] = (uint32_t) dmaCh;
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}
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/* Freqeuency mearure reference and target clock sources */
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typedef enum {
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FREQMSR_MAIN_OSC = 0, /*!< System oscillator */
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FREQMSR_IRC, /*!< Internal RC (IRC) oscillator */
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FREQMSR_WDOSC, /*!< Watchdog oscillator */
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FREQMSR_32KHZOSC, /*!< 32KHz (RTC) oscillator rate */
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FREQMSR_USB_FTOGGLE, /*!< USB FTOGGLE rate */
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FREQMSR_PIO0_5, /*!< External pin PIO0_5 as input rate */
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FREQMSR_PIO0_19, /*!< External pin PIO0_19 as input rate */
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FREQMSR_PIO0_30, /*!< External pin PIO0_30 as input rate */
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FREQMSR_PIO1_27 /*!< External pin PIO1_27 as input rate */
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} FREQMSR_SRC_T;
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/**
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* @brief Selects a reference clock used with the frequency measure function
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* @param ref : Frequency measure function reference clock
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* @return Nothing
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*/
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STATIC INLINE void Chip_INMUX_SetFreqMeasRefClock(FREQMSR_SRC_T ref)
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{
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LPC_INMUX->FREQMEAS_REF = (uint32_t) ref;
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}
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/**
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* @brief Selects a target clock used with the frequency measure function
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* @param targ : Frequency measure function reference clock
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* @return Nothing
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*/
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STATIC INLINE void Chip_INMUX_SetFreqMeasTargClock(FREQMSR_SRC_T targ)
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{
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LPC_INMUX->FREQMEAS_TARGET = (uint32_t) targ;
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}
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INMUX_15XX_H_ */
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